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| INTEGRATED CIRCUITS DATA SHEET TDA837x family I2C-bus controlled economy PAL/NTSC and NTSC TV-processors Preliminary specification File under Integrated Circuits, IC02 1997 Jul 01 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors FEATURES Available in all ICs: * Vision IF amplifier with high sensitivity and good figures for differential phase and gain * PLL demodulator for the IF signal * Alignment-free sound demodulator * Flexible source selection with a CVBS input for the internal signal and Y/C or CVBS input for the external signal * Audio switch * The output signal of the CVBS (Y/C) switch is externally available * Integrated chrominance trap and band-pass filters (auto-calibrated) * Luminance delay line integrated * A symmetrical peaking circuit in the luminance channel * Black stretching of non-standard CVBS or luminance signals * RGB control circuit with black current stabilization and white point adjustment * Linear RGB inputs and fast blanking * Horizontal synchronization with two control loops and alignment-free horizontal oscillator * Slow start and slow stop of the horizontal drive pulses * Vertical count-down circuit * Vertical driver optimized for DC-coupled vertical output stages * I2C-bus control of various functions * Low dissipation * Small amount of peripheral components compared with competition ICs. Table 1 TV receiver versions SDIP56 PACKAGE TV RECEIVERS ECONOMY PAL only PAL/NTSC (SECAM) NTSC TDA8374B TDA8374 and TDA8374A TDA8373 MID/HIGH END - TDA8375 and TDA8375A TDA8377 and TDA8377A GENERAL DESCRIPTION TDA837x family The various versions of the TDA837x series are I2C-bus controlled single-chip TV processors which are intended to be applied in PAL/NTSC (TDA8374 and TDA8375) and NTSC (TDA8373 and TDA8377) television receivers. All ICs are available in an SDIP56 package and some versions are also available in a QFP64 package. The ICs are pin compatible so that with one application board NTSC and PAL/NTSC (or multistandard together with the SECAM decoder TDA8395) receivers can be built. Functionally this IC series is split in to 2 categories: * Versions intended to be used in economy TV receivers with all basic functions * Versions with additional functions such as E-W geometry control, horizontal and vertical zoom function and YUV interface which are intended for TV receivers with 110 picture tubes. The various type numbers are given in Table 1. The detailed differences between the various ICs are given in Table 2. QFP64 PACKAGE ECONOMY TDA8374BH TDA8374AH - MID/HIGH END - TDA8375AH - 1997 Jul 01 2 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors Table 2 Differences between the various ICs IC VERSION (TDA) CIRCUITS 8373 Multistandard IF Automatic Volume Levelling (AVL) PAL decoder SECAM interface NTSC decoder Colour matrix PAL/NTSC (Japan) Colour matrix NTSC (USA/Japan) YUV interface Horizontal geometry Horizontal and vertical zoom QUICK REFERENCE DATA SYMBOL Supplies VP IP Input voltages V48,49(rms) V1(rms) V2(rms) V11(p-p) V10(p-p) V23-25(p-p) Output signals V6(p-p) I54 VoVSW V30(p-p) IF video output voltage (peak-to-peak value) tuner AGC output current range output signal level of video switch (peak-to-peak value) -(R - Y) output voltage (peak-to-peak value) - 0 - - 2.5 - 1.0 video IF amplifiers sensitivity (RMS value) sound IF amplifiers sensitivity (RMS value) external audio input voltage (RMS value) external CVBS/Y input voltage (peak-to-peak value) external chrominance input voltage (burst amplitude) (peak-to-peak value) RGB input voltage (peak-to-peak value) - - - - - - 70 1.0 supply voltage supply current - - 8.0 110 PARAMETER CONDITIONS MIN. - X - - X - X - - - 8374 X X X X X X - - - - 8374A(H) 8374B(H) - - X X X X - - - - - - X X X X - - - - 8375 X - X X X X - X X X TDA837x family 8375A(H) X - X X X X - X X X 8377 - - - - X - X X X X 8377A - - - - X - X X X X TYP. - - - - - - - - MAX. UNIT V mA V mV mV V V V 500 1.0 0.3 0.7 - 5 - - V mA V mV 525 1997 Jul 01 3 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors SYMBOL V29(p-p) V28(p-p) V19-21(p-p) I40 I46,47(p-p) I45(peak) PARAMETER -(B - Y) output voltage (peak-to-peak value) luminance output voltage (peak-to-peak value) RGB output signal amplitudes (peak-to-peak value) horizontal output current vertical output current (peak-to-peak value) E-W output current (peak value) TDA8375A, TDA8377A, TDA8375 and TDA8377 CONDITIONS - - - - - - MIN. TDA837x family TYP. 675 1.4 2.0 10 1 1.2 - - - - - - MAX. UNIT mV V V mA mA mA ORDERING INFORMATION TYPE NUMBER TDA837xA TDA837xH PACKAGE NAME SDIP56 QFP64 DESCRIPTION plastic shrink dual in-line package; 56 leads (600 mil) plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.7 mm; high stand-off height VERSION SOT400-1 SOT319-1 1997 Jul 01 4 ook, full pagewidth 1997 Jul 01 +8 V 54 53 43 44 12 37 14 7 8 9 42 41 AGC FOR IF AND TUNER tuner take-over point I2C-BUS TRANSCEIVER 40 50 REF IDENT VERTICAL GEOMETRY 46 47 51 MUTE VCO AND CONTROL 2nd LOOP AND HORIZONTAL OUTPUT VIDEO IDENTIFICATION CONTROL DACs 1 x 8 BITS 14 x 6 BITS 1 x 4 BITS SYNC SEPARATOR AND 1st LOOP HORIZONTAL/ VERTICAL DIVIDER BLOCK DIAGRAM Philips Semiconductors VCO ADJUSTMENT ADJ 3 4 48 49 VIF AMPLIFIER AND PLL DEMODULATOR 5 TDA8373 52 18 BLACK CURRENT STABILIZER AFC TRAP BAND-PASS VIDEO AMPLIFIER AND MUTE VERTICAL SYNC SEPARATOR BLACK STRETCHER 15 MUTE REF SW I2C-bus controlled economy PAL/NTSC and NTSC TV-processors 55 AFC white CONTR point BRI 22 21 20 19 5 PRE-AMPLIFIER AND MUTE CVBS Y/C SWITCH FILTER TUNING DELAY AND PEAKING SW HUE B-Y R-Y 34 3.6 MHz SOUND TRAP 30 29 PLL DEMODULATOR 13 17 38 10 11 16 33 36 CVBS SWITCH NTSC DECODER SAT G - Y MATRIX AND SAT CONTROL 32 2 45 AVL AND SWITCH AND VOLUME CONTROL RGB CONTROL AND OUTPUT 56 VOL SW 3 1 LIMITER 3 31 39 RGB MATRIX RGB INPUT AND SWITCH 23 24 25 26 MGK286 6 SOUND BAND-PASS The TDA8373 is only supplied in an SDIP package. TDA837x family Preliminary specification Fig.1 Block diagram of bus-controlled economy NTSC TV-processor TDA8373. ok, full pagewidth 1997 Jul 01 +8 V 54 53 43 40 14 I2C-BUS TRANSCEIVER tuner take-over point POL 50 REF IDENT VERTICAL GEOMETRY 46 47 51 POL MUTE VCO AND CONTROL 2nd LOOP AND HORIZONTAL OUTPUT 44 12 37 AGC FOR IF AND TUNER 7 8 9 42 41 CONTROL DACs 1 x 8 BITS 14 x 6 BITS 1 x 4 BITS SYNC SEPARATOR AND 1st LOOP HORIZONTAL/ VERTICAL DIVIDER Philips Semiconductors VCO ADJUSTMENT ADJ 3 4 48 49 VIF AMPLIFIER AND PLL DEMODULATOR VIDEO IDENTIFICATION 5 TDA8374 52 18 BLACK CURRENT STABILIZER AFC TRAP BAND-PASS VIDEO AMPLIFIER AND MUTE VERTICAL SYNC SEPARATOR BLACK STRETCHER 15 MUTE REF SW I2C-bus controlled economy PAL/NTSC and NTSC TV-processors 6 CVBS Y/C SWITCH FILTER TUNING DELAY AND PEAKING SW HUE B-Y R-Y 34 4.4 MHz SOUND TRAP 3.6 MHz TDA4665 30 29 CVBS SWITCH PAL/NTSC DECODER SAT 13 17 38 10 11 16 33 36 (51) 35 32 55 AFC white CONTR point BRI 22 21 20 19 RGB CONTROL AND OUTPUT 2 45 AVL AND SWITCH AND VOLUME CONTROL PRE-AMPLIFIER AND MUTE 56 VOL SW 3 1 LIMITER PLL DEMODULATOR G - Y MATRIX AND SAT CONTROL 31 3 RGB MATRIX RGB INPUT AND SWITCH 39 23 24 25 26 6 MGK287 SOUND BAND-PASS For most pins the QFP64 pinning is not indicated. TDA837x family Preliminary specification Fig.2 Block diagram of bus-controlled economy PAL/NTSC TV processor TDA8374. ook, full pagewidth 1997 Jul 01 +8 V 54 (7) 53 (6) 43 (59) 42 (58) 40 (56) E-W GEOMETRY (62) 45 41 (57) 7 (17) 8 (18) 9 44 12 37 14 (25,26) (60,61) (19) (22,23) (53) AGC FOR IF AND TUNER tuner take-over point I2C-BUS TRANSCEIVER POL REF IDENT VERTICAL GEOMETRY (63) 46 (64) 47 (4) 51 POL MUTE (3) 50 VCO AND CONTROL 2nd LOOP AND HORIZONTAL OUTPUT CONTROL DACs 1 x 8 BITS 18 x 6 BITS 1 x 4 BITS SYNC SEPARATOR AND 1st LOOP HORIZONTAL/ VERTICAL DIVIDER Philips Semiconductors VCO ADJUSTMENT ADJ 3 (13) 4 (14) 48 (1) 49 (2) VIF AMPLIFIER AND PLL DEMODULATOR VIDEO IDENTIFICATION 5 (15) TDA8375 (5) 52 (30) 18 BLACK CURRENT STABILIZER AFC TRAP BAND-PASS VIDEO AMPLIFIER AND MUTE VERTICAL SYNC SEPARATOR BLACK STRETCHER 15 (27) MUTE REF FILTER TUNING SW I2C-bus controlled economy PAL/NTSC and NTSC TV-processors 55 (8) AFC white CONTR point BRI (34) 22 (33) 21 7 CVBS Y/C SWITCH DELAY PLUS PEAKING PLUS CORING SW HUE B-Y R-Y CVBS SWITCH PAL/NTSC DECODER SAT G - Y MATRIX AND SAT CONTROL (48) (47) 32 31 (24) 13 (51) 35 3.6 MHz 4.4 MHz SOUND TRAP (29) (54) 17 38 (20) (21) (28) (49) 10 11 16 33 (52) 36 (50) (46) (45) 34 30 29 TDA4665 2 (11) SWITCH AND VOLUME CONTROL PRE-AMPLIFIER AND MUTE (32) 20 (31) 19 RGB CONTROL AND OUTPUT 56 (9) VOL SW 3 1 (10) LIMITER PLL DEMODULATOR 3 RGB MATRIX RGB INPUT AND SWITCH (40) (39) (55) 28 27 39 (35) (36) (37) 23 24 25 (38) 26 (16) 6 MGK288 SOUND BAND-PASS TDA837x family Preliminary specification Fig.3 Block diagram of bus-controlled economy PAL/NTSC TV processor TDA8375. full pagewidth 1997 Jul 01 +8 V 54 tuner take-over point I2C-BUS TRANSCEIVER E-W GEOMETRY 45 50 REF IDENT VERTICAL GEOMETRY 46 47 51 MUTE VCO AND CONTROL 2nd LOOP AND HORIZONTAL OUTPUT 53 7 43 44 12 37 14 9 42 41 40 8 CONTROL DACs 1 x 8 BITS 18 x 6 BITS 1 x 4 BITS SYNC SEPARATOR AND 1st LOOP HORIZONTAL/ VERTICAL DIVIDER Philips Semiconductors VCO ADJUSTMENT ADJ AGC FOR IF AND TUNER 3 4 48 49 VIF AMPLIFIER AND PLL DEMODULATOR VIDEO IDENTIFICATION 5 TDA8377 52 18 BLACK CURRENT STABILIZER white CONTR point BRI AFC TRAP BAND-PASS VIDEO AMPLIFIER AND MUTE VERTICAL SYNC SEPARATOR BLACK STRETCHER 15 MUTE REF FILTER TUNING SW I2C-bus controlled economy PAL/NTSC and NTSC TV-processors 55 AFC 22 21 8 CVBS Y/C SWITCH DELAY PLUS PEAKING PLUS CORING SW HUE B-Y R-Y 34 3.6 MHz SOUND TRAP 30 29 CVBS SWITCH NTSC DECODER SAT G - Y MATRIX AND SAT CONTROL 32 31 13 17 38 10 11 16 33 36 2 SWITCH AND VOLUME CONTROL PRE-AMPLIFIER AND MUTE 20 19 RGB CONTROL AND OUTPUT 56 VOL SW 3 1 LIMITER PLL DEMODULATOR 3 RGB MATRIX RGB INPUT AND SWITCH 28 27 39 23 24 25 26 6 MGK289 SOUND BAND-PASS The TDA8377 is only supplied in an SDIP package. TDA837x family Preliminary specification Fig.4 Block diagram of bus-controlled economy NTSC TV processor TDA8377. Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors PINNING PIN SYMBOL SDIP56 SIF AUDI VCO1 VCO2 PLL IFVO SCL SDA DECBG CHROMA CVBS/Y VP1 CVBSint GND1 AUDO DECFT CVBSext BLKIN BO GO RO BCLIN RI GI BI RGBIN YIN YOUT BYO RYO RYI BYI SECref XTAL1 XTAL2 LFBP VP2 CVBSO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27(2) 28 29 30 31 32 33(1) 34 35(1) 36 37 38 QFP64 10 11 13 14 15 16 17 18 19 20 21 22 and 23 24 25 and 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 45 46 47 48 49 50 51 52 53 54 sound IF input external audio input IF VCO 1 tuned circuit IF VCO 2 tuned circuit PLL loop filter IF video output serial clock input (I2C-bus) serial data input/output (I2C-bus) band gap decoupling chrominance input CVBS/Y input main supply voltage (+8 V) internal CVBS input ground audio output decoupling filter tuning external CVBS input black current input blue output green output red output beam current input red input green input blue input RGB insertion input luminance input luminance output (B - Y) output (R - Y) output (R - Y) input (B - Y) input SECAM reference output 3.58 MHz crystal connection 4.43 MHz crystal connection loop filter burst phase detector TDA837x family DESCRIPTION horizontal oscillator supply voltage (+8 V) CVBS output 1997 Jul 01 9 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors PIN SYMBOL SDIP56 BLPH HOUT FBI/SCO PH2 PH1 GND2 EWD VDOB VDOA IFIN1 IFIN2 EHT/PRO VSAW Iref DECAGC AGCOUT AUDEEM DEC i.c. i.c. i.c. i.c. i.c. Notes 39 40 41 42 43 44 45(2) 46 47 48 49 50 51 52 53 54 55 56 - - - - - QFP64 55 56 57 58 59 60 and 61 62 63 64 1 2 3 4 5 6 7 8 9 12 41 42 43 44 black peak hold capacitor horizontal drive output flyback input and sandcastle output phase 2 filter/protection phase 1 filter ground 2 east-west drive output vertical drive output B vertical drive output A IF input 1 IF input 2 EHT/overvoltage protection input vertical sawtooth capacitor reference current input AGC decoupling capacitor tuner AGC output audio deemphasis decoupling sound demodulator internally connected internally connected internally connected internally connected internally connected TDA837x family DESCRIPTION 1. In the TDA8373 and TDA8377 pin 35 (4.43 MHz crystal) is internally connected and pin 33 is just a subcarrier output which can be used as a reference signal for comb filter ICs. 2. In the TDA8373 and TDA8374 the following pins are different (SDIP56): Pin 27: not connected; Pin 45: AVL capacitor. 1997 Jul 01 10 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family handbook, halfpage SIF AUDI VCO1 VCO2 PLL IFVO SCL SDA DECBG 1 2 3 4 5 6 7 8 9 56 DEC 55 AUDEEM 54 AGCOUT 53 DECAGC 52 Iref 51 VSAW 50 EHT/PRO 49 IFIN2 48 IFIN1 47 VDOA 46 VDOB 45 EWD 44 GND2 43 PH1 CHROMA 10 CVBS/Y 11 VP1 12 CVBSint 13 GND1 14 TDA837x AUDO 15 DECFT 16 CVBSext 17 BLKIN 18 BO 19 GO 20 RO 21 BCLIN 22 RI 23 GI 24 BI 25 RGBIN 26 YIN 27 YOUT 28 MGK284 42 PH2 41 FBI/SCO 40 HOUT 39 BLPH 38 CVBSO 37 VP2 36 LFBP 35 XTAL2 34 XTAL1 33 SECref 32 BYI 31 RYI 30 RYO 29 BYO Fig.5 Pin configuration (SDIP56). 1997 Jul 01 11 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family 57 FBI/SCO 54 CVBSO IFIN1 1 IFIN2 2 EHT/PRO 3 VSAW 4 Iref 5 DECAGC 6 AGCOUT 7 AUDEEM 8 49 SECref 48 BYI 47 RYI 46 RYO 45 BYO 44 i.c. 43 i.c. 42 i.c. 41 i.c. 40 YOUT 39 YIN 38 RGBIN 37 BI 36 GI 35 RI 34 BCLIN 33 RO GO 32 handbook, full pagewidth 51 XTAL2 BLKIN 30 TDA837xH DEC 9 SIF 10 AUDI 11 i.c. 12 VCO1 13 VCO2 14 PLL 15 IFVO 16 CHROMA 20 CVBS/Y 21 VP1 22 VP1 23 CVBSint 24 GND1 25 GND1 26 AUDO 27 DECFT 28 CVBSext 29 SCL 17 SDA 18 DECBG 19 BO 31 50 XTAL1 64 VDOA 63 VDOB 56 HOUT 61 GND2 60 GND2 55 BLPH 52 LFBP 62 EWD 59 PH1 58 PH2 53 VP2 MGK285 Fig.6 Pin configuration (QFP64). 1997 Jul 01 12 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors FUNCTIONAL DESCRIPTION Vision IF amplifier The IF amplifier contains 3 AC-coupled control stages with a total gain control range which is higher than 66 dB. The sensitivity of the circuit is comparable with that of modern IF-ICs. The video signal is demodulated by a PLL carrier regenerator. This circuit contains a frequency detector and a phase detector. During acquisition the frequency detector will tune the VCO to the correct frequency. The initial adjustment of the oscillator is realized via the I2C-bus. The switching, between SECAM L and L', can also be realized via the I2C-bus. After lock-in the phase detector controls the VCO so that a stable phase relationship between the VCO and the input signal is achieved. The VCO operates at twice the IF frequency. The reference signal for the demodulator is obtained by using a frequency divider circuit. The AFC output is obtained by using the VCO control voltage of the PLL and can be read via the I2C-bus. For fast search tuning systems the window of the AFC can be increased by a factor of 3. The setting is realized with the AFW bit. Depending on the device type the AGC detector operates on top-sync level (single standard versions) or on top-sync and top-white level (multistandard versions). The demodulation polarity is switched via the I2C-bus. The AGC detector time constant capacitor is connected externally. This is mainly because of the flexibility of the application. The time constant of the AGC system during positive modulation is rather long, this is to avoid visible variations of the signal amplitude. To improve the speed of the AGC system, a circuit has been included which detects whether the AGC detector is activated every frame period. When, during 3 frame periods, no action is detected the speed of the system is increased. For signals without peak-white information the system switches automatically TDA837x family to a gated black level AGC. Because a black level clamp pulse is required for this method of operation the circuit will only switch to black level AGC in the internal mode. The circuits contain a second fast video identification circuit which is independent of the synchronization identification circuit. Consequently, search tuning is also possible when the display section of the receiver is used as a monitor. However, this identification circuit cannot be made as sensitive as the slower sync identification circuit (SL) and it is recommended to use both identification outputs to obtain a reliable search system. The identification output is applied to the tuning system via the I2C-bus. The input of the identification circuit is connected to pin 13, the internal CVBS input (see Fig.1). This has the advantage that the identification circuit can also be made operative when a scrambled signal is received [descrambler connected between the IF video output (pin 6) and pin 13]. A second advantage is that the identification circuit can be used when the IF amplifier is not used (e.g. with built-in satellite tuners). The video identification circuit can also be used to identify the selected CBVS or Y/C signal. The switching between the two modes can be realized with bit VIM. Video switches The circuit has two CVBS inputs (CVBSint and CVBSext) and a Y/C input. When the Y/C input is not required pin 11 can be used as the third CVBS input. The switch configuration is illustrated in Fig.7. The selection of the various sources is made via the I2C-bus. The output signal of the CVBS switch is externally available and can be used to drive the teletext decoder, the SECAM add-on decoder and a comb filter. In applications with comb filters a Y/C input is only possible when additional switches are added. In applications without comb filters the Y/C input signal can be switched to the CVBS output. 1997 Jul 01 13 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family handbook, full pagewidth IDENT VIM to luminance/ sync processing to chrominance processing VIDEO IDENTIFICATION + S0 S0 S5 S1 S1 S6 S2 S3 S7 S4 S8 TDA837x 13 CVBSint 17 CVBSext 11 CVBS/Y 10 CHROMA 38 MGK301 CVBSO Fig.7 Configuration CVBS switch and interfacing of video identification. Sound circuit The sound band-pass and trap filters have to be connected externally. The filtered intercarrier signal is fed to a limiter circuit and is demodulated by a PLL demodulator. This PLL circuit automatically tunes to the incoming carrier signal, hence no adjustment is required. The volume is controlled via the I2C-bus. The de-emphasis capacitor has to be connected externally. The non-controlled audio signal can be obtained from this pin (pin 55) (via a buffer stage). The FM demodulator can be muted via the I2C-bus. This function can be used to switch-off the sound during a channel change so that high output peaks are prevented (also on the de-emphasis output). The TDA8373 and TDA8374 contain an Automatic Volume Levelling (AVL) circuit which automatically stabilizes the audio output signal to a certain level which can be set by the user via the volume control. This function prevents big audio output fluctuations due to variations of the modulation depth of the transmitter. The AVL function can be activated via the I2C-bus. Synchronization circuit The sync separator is preceded by a controlled amplifier which adjusts the sync pulse amplitude to a fixed level. These pulses are fed to the slicing stage which operates at 50% of the amplitude. The separated sync pulses are fed to the first phase detector and to the coincidence detector. The coincidence detector is used to detect whether the line oscillator is synchronized and can also be used for transmitter identification. The circuit can be made less sensitive by using the STM bit. This mode can be used during search tuning to ensure that the tuning system will not stop at very weak input signals. The first PLL has a very high static steepness so that the phase of the picture is independent of the line frequency. The line oscillator operates at twice the line frequency. The oscillator capacitor is internal. Because of the spread of internal components an automatic calibration circuit has been added to the IC. The circuit compares the oscillator frequency with that of the crystal oscillator in the colour decoder. 1997 Jul 01 14 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors This results in a free-running frequency which deviates less than 2% from the typical value. When the IC is switched on the horizontal output signal is suppressed and the oscillator is calibrated as soon as all subaddress bytes have been sent. When the frequency of the oscillator is correct the horizontal drive signal is switched on. To obtain a smooth switching on and switching off behaviour of the horizontal output stage the horizontal output frequency is doubled during switch-on and switch-off (slow start/stop). During that time the duty cycle of the output pulse has such a value that maximum safety is obtained for the output stage. To protect the horizontal output transistor, the horizontal drive is immediately switched off (via the slow stop procedure) when a power-on reset is detected. The drive signal is switched on again when the normal switch-on procedure is followed, i.e. all subaddress bytes must be sent and, after calibration, the horizontal drive signal will be released again via the slow start procedure. When the coincidence detector indicates an out-of-lock situation the calibration procedure is repeated. The circuit has a second control loop to generate the drive pulses for the horizontal driver stage. The horizontal output is gated with the flyback pulse so that the horizontal output transistor cannot be switched on during the flyback time. Adjustments can be made to the horizontal shift, vertical shift, vertical slope, vertical amplitude and the S-correction via the I2C-bus. In the TDA8375A, TDA8377A, TDA8375 and TDA8377 the E-W drive can also be adjusted via the I2C-bus. The TDA8375 and TDA8377 have a flexible zoom adjustment possibility for the vertical and horizontal deflection. When the horizontal scan is reduced to display 4 : 3 pictures on a 16 : 9 picture tube an accurate video blanking can be switched on to obtain well defined edges on the screen. The geometry processor has a differential output for the vertical drive signal and a single-ended output for the E-W drive (TDA8375A, TDA8377A, TDA8375 and TDA8377). Overvoltage conditions (X-ray protection) can be detected via the EHT tracking pin. When an overvoltage condition is detected the horizontal output drive signal will be switched off via the slow stop procedure. However, it is also possible that the drive is not switched off and that just a protection indication is given in the I2C-bus output byte. The choice is made via the input bit PRD. The ICs have a second protection input on the phase-2 filter capacitor pin. When this input is activated the drive signal is switched off immediately (without slow stop) and switched on again via the slow start procedure. TDA837x family For this reason this protection input can be used as `flash protection'. The drive pulses for the vertical sawtooth generator are obtained from a vertical countdown circuit. This countdown circuit has various windows depending on the incoming signal (50 or 60 Hz and standard or non-standard). The countdown circuit can be forced in various modes via the I2C-bus. To obtain short switching times of the countdown circuit during a channel change the divider can be forced in the search window using the NCIN bit. The vertical deflection can be set in the de-interlace mode via the I2C-bus. To avoid damage of the picture tube when the vertical deflection fails, the guard output current of the TDA8350 and TDA8351 can be supplied to the beam current limiting input. When a failure is detected the RGB outputs are blanked and a bit is set (NDF) in the status byte of the I2C-bus. When no vertical deflection output stage is connected this guard circuit will also blank the output signals. This can be overruled using the EVG bit. Chrominance and luminance processing The circuit contains a chrominance band-pass and trap circuit. The filters are realized by using gyrator circuits. They are automatically calibrated by comparing the tuning frequency with the crystal frequency of the decoder. The luminance delay line and the delay for the peaking circuit are also realized by using gyrator circuits. The centre frequency of the chrominance band-pass filter is 10% higher than the subcarrier frequency. This compensates for the high frequency attenuation of the IF saw filter. During SECAM reception the centre frequency of the chrominance trap is reduced to obtain a better suppression of the SECAM carrier frequencies. All ICs have a black stretcher circuit which corrects the black level for incoming video signals which have a deviation between the black level and the blanking level (back porch). The TDA8375A, TDA8377A, TDA8375 and TDA8377 have a defeatable coring function in the peaking circuit. Some of the ICs have a YUV interface so that picture improvement ICs such as the TDA9170 (contrast improvement), TDA9177 (sharpness improvement) and TDA4556 and TDA4566 (CTI) can be applied. When the TDA4556 or TDA4566 is applied it is possible to increase the gain of the luminance channel by using the GAI bit in subaddress 03 so that the resulting RGB output signals will not be affected. 1997 Jul 01 15 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors Colour decoder Depending on the IC type the colour decoder can decode NTSC signals (TDA8373 and TDA8377) or PAL/NTSC signals (TDA8374 and TDA8375). The circuit contains an alignment-free crystal oscillator, a killer circuit and two colour difference demodulators. The 90 phase shift for the reference signal is made internally. The TDA8373 and TDA8377 contain an Automatic Colour Limiting (ACL) circuit which prevents over saturation occurring when signals with a high chroma-to-burst ratio are received. This ACL function is also available in the TDA8374 and TDA8375, however, it is only active during the reception of NTSC signals. The TDA8373 and TDA8377 have a switchable colour difference matrix (via the I2C-bus) so that the colour reproduction can be adapted to the market requirements. In the TDA8374 and TDA8375 the colour difference matrix switches automatically between PAL and NTSC, however, it is also possible to fix the matrix in the PAL standard. The TDA8374 and TDA8375 can operate in conjunction with the SECAM decoder TDA8395 so that an automatic multistandard decoder can be realized. The subcarrier reference output for the SECAM decoder can also be used as a reference signal for a comb filter. Consequently, the reference signal is continuously available when PAL or NTSC signals are detected and only present during the vertical retrace period when a SECAM signal is detected. Which standard the TDA8374 and TDA8375 can decode depends on the external crystals. The crystal to be connected to pin 34 must have a frequency of 3.5 MHz (NTSC-M, PAL-M or PAL-N). Pin 35 can handle crystals with a frequency of 4.4 and 3.5 MHz. Because the crystal frequency is used to tune the line oscillator, the value of the crystal frequency must be communicated to the IC via the I2C-bus. It is also possible to use the IC in the so called `3-norma' mode for South America. In that event one crystal must be connected to pin 35 and the other two to pin 34. Switching between the 2 latter crystals must be performed externally. Consequently, the search loop of the decoder must be controlled by the microcontroller. To prevent calibration problems of the horizontal oscillator the external switching between the two crystals should be performed when the oscillator is forced to pin 35. TDA837x family For a reliable calibration of the horizontal oscillator it is very important that the crystal indication bits (XA and XB) are not corrupted. For this reason the crystal bits can be read in the output bytes so that the software can check the I2C-bus transmission. RGB output circuit and black current stabilization The colour difference signals are matrixed with the luminance signal to obtain the RGB signals. Linear amplifiers have been chosen for the RGB inputs so that the circuit is suited for signals that are input from the SCART connector. The insertion blanking can be switched on or off using the IE1 bit. To ascertain whether the insertion pin has a (continuous) HIGH level or not can be read via the IN1 bit. The contrast and brightness control operate on internal and external signals. The output signal has an amplitude of approximately 2 V (black-to-white) at nominal input signals and nominal settings of the controls. To increase the flexibility of the IC it is possible to add OSD and/or teletext signals directly at the RGB outputs. This insertion mode is controlled via the insertion input. The action to switch the RGB outputs to black has some delay which must be compensated for externally. The black current stabilization is realized by using a feedback from the video output amplifiers to the RGB control circuit. The black current of the 3 guns of the picture tube is internally measured and stabilized. The black level control is active during 4 lines at the end of the vertical blanking. The vertical blanking is adapted to the incoming CVBS signal (50 or 60 Hz). When the flyback time of the vertical output stage is longer than the 60 Hz blanking time, or when additional lines need to be blanked (e.g. for close captioning lines) the blanking can be increased to the same value as that of the 50 Hz blanking. This can be set using the LBM bit. The leakage current is measured during the first line and, during the following 3 lines, the 3 guns are adjusted to the required level. The maximum acceptable leakage current is 100 A. The nominal value of the black current is 10 A. The ratio of the currents for the various guns automatically tracks with the white point adjustment so that the background colour is the same as the adjusted white point. 1997 Jul 01 16 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors The input impedance of the black current measuring pin is 14 k. To prevent the voltage on this pin exceeding the supply voltage during scan an internal protection diode has been included. When the TV receiver is switched on the black current stabilization circuit is not active, the RGB outputs are blanked and the beam current limiting input pin is short-circuited. Only during the measuring lines will the outputs supply a voltage of 4.2 V to the video output stage I2C-bus specification Table 3 A6 1 Slave address (8A) A5 0 A4 0 A3 0 A2 1 A1 0 TDA837x family to ascertain whether the picture tube is warming up. As soon as the current supplied to the measuring input exceeds a value of 190 A the stabilization circuit will be activated. After a waiting time of approximately 0.8 s the blanking and beam current limiting input pins are released. The remaining switch-on behaviour of the picture is determined by the external time constant of the beam current limiting network. A0 1 R/W I/O The slave address is identical for all types. The subaddresses of the various types are slightly different. The list of subaddresses for each type is given in Tables 4, 6, 8 and 10. START-UP PROCEDURE Read the status bytes until POR = 0 and send all subaddress bytes. The horizontal output signal is switched on when the oscillator is calibrated. Each time before the data in the IC is refreshed, the status bytes must be read. If POR = 1, then the procedure given above must be carried out to restart the IC. When this procedure is not followed the horizontal frequency in the TDA8374 and TDA8375 may be incorrect after power-up or a power dip. 1997 Jul 01 17 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA8373 TDA837x family Valid subaddresses: 00 to 16 (subaddresses 04 to 07 are not used), subaddress FE is reserved for test purposes. Auto-increment mode available for subaddresses. Table 4 Inputs SUB ADDRESS 00 01 02 03 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 Output status bytes (note 1) OUTPUT ADDRESS 00 01 02 Note 1. X = don't care. D7 POR NDF X D6 X IN1 X D5 X X X D4 SL IFI IVW D3 XPR AFA X D2 CD2 AFB ID2 D1 CD1 SXA ID1 D0 CD0 SXB ID0 DATA BYTE D7 INA 0 AVL VIM NCIN VID 0 SBL 0 0 MAT 0 RBL IE1 AFW 0 SM L'FA 0 D6 INB 0 AKB GAI STM LBM EVG PRD 0 0 0 0 0 0 IFS VSW FAV A6 0 D5 INC DL A5 A5 A5 A5 A5 A5 A5 A5 A5 0 A5 A5 A5 A5 A5 A5 0 D4 0 STB A4 A4 A4 A4 A4 A4 A4 A4 A4 0 A4 A4 A4 A4 A4 A4 0 D3 FOA POC A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 0 D2 FOB 0 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 0 D1 0 1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 0 D0 0 1 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 0 FUNCTION Control 0 Control 1 Hue Horizontal Shift (HS) Vertical Slope (VS) Vertical Amplitude (VA) S-Correction (SC) Vertical shift (VSH) White point R White point G White point B Peaking Brightness Saturation Contrast AGC takeover Volume control Adjustment IF-PLL Spare Table 5 1997 Jul 01 18 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA8374, TDA8374AH and TDA8374BH TDA837x family Valid subaddresses: 00 to 16 (subaddresses 04 to 07 are not used), subaddress FE is reserved for test purposes. Auto-increment mode available for subaddresses. Table 6 Inputs (notes 1 and 2) SUB ADDRESS 00 01 02 03 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 DATA BYTE D7 INA FORF AVL VIM NCIN VID 0 SBL 0 0 MAT 0 RBL IE1 AFW MOD SM L'FA 0 D6 INB FORS AKB GAI STM LBM EVG PRD 0 0 0 0 0 0 IFS VSW FAV A6 0 D5 INC DL A5 A5 A5 A5 A5 A5 A5 A5 A5 0 A5 A5 A5 A5 A5 A5 0 D4 0 STB A4 A4 A4 A4 A4 A4 A4 A4 A4 0 A4 A4 A4 A4 A4 A4 0 D3 FOA POC A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 0 D2 FOB CM2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 0 D1 XA CM1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 0 D0 XB CM0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 0 FUNCTION Control 0 Control 1 Hue Horizontal Shift (HS) Vertical Slope (VS) Vertical Amplitude (VA) S-Correction (SC) Vertical shift (VSH) White point R White point G White point B Peaking Brightness Saturation Contrast AGC takeover Volume control Adjustment IF-PLL Spare Notes 1. The AVL and MOD bit are not available in the TDA8374A. 2. In the TDA8374B the AVL and MOD bit is also missing and the CM0 to CM2 and CD0 to CD2 bits have less possibilities because this IC can only decode PAL or PAL/SECAM signals (when the TDA8395 is applied). Table 7 Output status bytes (note 1) OUTPUT ADDRESS 00 01 02 Note 1. X = don't care. D7 POR NDF X D6 FSI IN1 X D5 X X X D4 SL IFI IVW D3 XPR AFA X D2 CD2 AFB ID2 D1 CD1 SXA ID1 D0 CD0 SXB ID0 1997 Jul 01 19 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA8375 and TDA8375AH TDA837x family Valid subaddresses: 00 to 16, subaddress FE is reserved for test purposes. Auto-increment mode available for subaddresses. Table 8 Inputs FUNCTION Control 0 Control 1 Hue Horizontal Shift (HS) E-W width (EW) E-W Parabola/Width (PW) E-W Corner Parabola (CP) E-W trapezium (TC) Vertical Slope (VS) Vertical Amplitude (VA) S-Correction (SC) Vertical shift (VSH) White point R White point G White point B Peaking Brightness Saturation Contrast AGC takeover Volume control Adjustment IF-PLL Vertical zoom (VX)(1) Note 1. The vertical zoom byte and the HBL bit are active only in the TDA8375. Table 9 Output status bytes (note 1) OUTPUT ADDRESS 00 01 02 Note 1. X = don't care. D7 POR NDF X D6 FSI IN1 X D5 X X X D4 SL IFI IVW D3 XPR AFA X D2 CD2 AFB ID2 D1 CD1 SXA ID1 D0 CD0 SXB ID0 SUB ADDRESS 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 DATA BYTE D7 INA FORF HBL VIM 0 0 0 0 NCIN VID HCO SBL 0 0 MAT 0 RBL IE1 AFW MOD SM L'FA 0 D6 INB FORS AKB GAI 0 0 0 0 STM LBM EVG PRD 0 0 0 0 COR 0 IFS VSW FAV A6 0 D5 INC DL A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 0 A5 A5 A5 A5 A5 A5 A5 D4 0 STB A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 0 A4 A4 A4 A4 A4 A4 A4 D3 FOA POC A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 D2 FOB CM2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 D1 XA CM1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 D0 XB CM0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 1997 Jul 01 20 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA8377 and TDA8377A TDA837x family Valid subaddresses: 00 to 16, subaddress FE is reserved for test purposes. Auto-increment mode available for subaddresses. Table 10 Inputs FUNCTION Control 0 Control 1 Hue Horizontal Shift (HS) E-W width (EW) E-W Parabola/Width (PW) E-W Corner Parabola (CP) E-W trapezium (TC) Vertical Slope (VS) Vertical Amplitude (VA) S-Correction (SC) Vertical shift (VSH) White point R White point G White point B Peaking Brightness Saturation Contrast AGC takeover Volume control Adjustment IF-PLL Vertical zoom (VX)(1) Note 1. The vertical zoom byte and the HBL bit are active only in the TDA8377. Table 11 Output status bytes (note 1) OUTPUT ADDRESS 00 01 02 Note 1. X = don't care. D7 POR NDF X D6 X IN1 X D5 X X X D4 SL IFI IVW D3 XPR AFA X D2 CD2 AFB ID2 D1 CD1 SXA ID1 D0 CD0 SXB ID0 SUB ADDRESS 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 DATA BYTE D7 INA 0 HBL VIM 0 0 0 0 NCIN VID HCO SBL 0 0 MAT 0 RBL IE1 AFW 0 SM L'FA 0 D6 INB 0 AKB GAI 0 0 0 0 STM 0 EVG PRD 0 0 0 0 COR 0 IFS VSW FAV A6 0 D5 INC DL A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 A5 0 A5 A5 A5 A5 A5 A5 A5 D4 0 STB A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 A4 0 A4 A4 A4 A4 A4 A4 A4 D3 FOA POC A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 A3 D2 FOB 0 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 D1 0 1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 D0 1 1 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 1997 Jul 01 21 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors INPUT CONTROL BITS Table 12 Source select INA 0 0 0 0 1 1 INB 0 0 1 1 0 1 INC 0 1 0 1 0 0 SELECTED SIGNALS (DECODER AND AUDIO) internal CVBS plus audio external CVBS plus audio Y/C plus external audio CVBS3 plus external audio Y/C plus internal audio Y/C plus external audio TDA837x family SWITCH OUTPUT internal CVBS external CVBS Y/C (Y plus C) CVBS3 internal CVBS external CVBS Table 13 Phase 1 (-1) time constant FOA 0 0 1 1 Table 14 Crystal indication XA 0 0 1 1 XB 0 1 0 1 CRYSTAL two 3.6 MHz crystals one 3.6 MHz crystal (pin 34) one 4.4 MHz crystal (pin 35) 3.6 MHz and 4.4 MHz crystals (pins 34 and 35) FOB 0 1 0 1 MODE normal slow and gated slow/fast and gated fast Table 15 Forced field frequency TDA8374 and TDA8375 FORF 0 0 1 1 Note 1. When switched to this mode while locked to a 50 Hz signal, the divider will only switch to forced 60 Hz when an out-of-sync is detected in the horizontal PLL. FORS 0 1 0 1 FIELD FREQUENCY auto (60 Hz when line not synchronized) 60 Hz; note 1 keep last detected field frequency auto (50 Hz when line not synchronized) 1997 Jul 01 22 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors Table 16 Interlace DL 0 1 interlace de-interlace STATUS TDA837x family Table 22 Black current stabilization AKB 0 1 STABILIZATION black-current stabilization on black-current stabilization off Table 17 Standby STB 0 1 standby normal MODE Table 23 Video identification mode VIM 0 1 VIDEO IDENT MODE video identification coupled to the internal CVBS input (pin 13) video identification coupled to the selected CVBS input Table 18 Synchronization mode POC 0 1 MODE synchronization active synchronization not active Table 24 Gain of luminance channel GAI 0 GAIN normal gain of luminance channel [V27 = 1.0 V (b-w)] high gain of luminance channel [V27 = 0.45 V (p-p)] Table 19 Colour decoder mode 1 CM2 0 0 0 0 1 1 1 1 CM1 0 0 1 1 0 0 1 1 CM0 0 1 0 1 0 1 0 1 DECODER MODE not forced, own intelligence, two crystals forced crystal pin 34 (PAL/NTSC) forced crystal pin 34 (PAL) forced crystal pin 34 (NTSC) forced crystal pin 35 (PAL/NTSC) forced crystal pin 35 (PAL) forced crystal pin 35 (NTSC) forced SECAM crystal pin 35 Table 25 Vertical divider mode NCIN 0 1 VERTICAL DIVIDER MODE normal operation of the vertical divider vertical divider switched to search window Table 26 Search tuning mode STM 0 1 SEARCH TUNING MODE normal operation reduced sensitivity of the coincidence detector (bit SL) Table 20 Automatic volume levelling (TDA8373 and TDA8374) AVL 0 1 LEVEL automatic volume levelling not active automatic volume levelling active Table 27 Video identification mode VID 0 1 VIDEO IDENT MODE video identification switches phase 1 loop on and off video identification not active Table 21 RGB blanking mode (TDA8375 and TDA8377) Table 28 Long blanking mode (TDA8374 and TDA8375) HBL 0 1 MODE normal blanking with horizontal blanking pulse wider blanking to obtain well defined edges LBM 0 1 BLANKING MODE blanking adapted to standard (50 or 60 Hz) fixed blanking in accordance with 50 Hz standard 1997 Jul 01 23 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors Table 29 EHT tracking mode (TDA8375 and TDA8377) HCO 0 1 TRACKING MODE EHT tracking only on vertical EHT tracking on vertical and E-W TDA837x family Table 36 Noise coring peaking (TDA8375 and TDA8377)) COR 0 1 noise coring off noise coring on MODE Table 30 Enable vertical guard (RGB blanking) EVG 0 1 VERTICAL GUARD MODE vertical guard not active vertical guard active Table 37 Enable fast blanking IE1 0 1 Table 31 Service blanking SBL 0 1 SERVICE BLANKING MODE service blanking off service blanking on Table 38 AFC window AFW 0 1 Table 32 Overvoltage input mode PRD 0 1 OVERVOLTAGE MODE overvoltage detection mode overvoltage protection mode Table 39 IF sensitivity IFS 0 1 Table 33 PAL/NTSC or NTSC matrix (TDA8374 and TDA8375) MAT 0 1 MATRIX matrix adapted to standard (NTSC = Japanese) PAL matrix Table 41 Video mute Table 34 PAL/NTSC or NTSC matrix (TDA8373 and TDA8377) MAT 0 1 Japanese matrix USA matrix Table 42 Sound mute SM MODE blanking not active blanking active 0 1 normal operation sound muted STATE MATRIX VSW 0 1 normal operation IF video signal switched off STATE IF SENSITIVITY normal sensitivity reduced sensitivity normal window enlarged window AFC WINDOW FAST BLANKING fast blanking not active fast blanking active Table 40 Modulation standard (TDA8374 and TDA8375) MOD 0 1 MODULATION negative modulation positive modulation Table 35 RGB blanking RBL 0 1 1997 Jul 01 24 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors Table 43 Fixed audio volume FAV 0 1 STATE normal volume control audio output level fixed Table 50 Output vertical guard NDF 0 1 TDA837x family VERTICAL OUTPUT STAGE vertical output stage OK failure in vertical output stage Table 44 Demodulator frequency adjustment L'FA 0 1 STATE normal IF frequency frequency shift for L' standard Table 51 Indication RGB insertion IN1 0 1 no insertion insertion RGB INSERTION OUTPUT CONTROL BITS Table 45 Power-on-reset POR 0 1 normal mode power-down mode MODE Table 52 Output video identification IFI 0 1 VIDEO SIGNAL no video signal identified video signal identified Table 53 AFC output AFA 0 0 1 1 AFB 0 1 0 1 CONDITION outside window; too low outside window; too high inside window; below reference inside window; above reference Table 46 Field frequency (TDA8374 and TDA8375) FSI 0 1 50 Hz 60 Hz FREQUENCY Table 47 Phase 1 lock indication SL 0 1 not locked locked INDICATION Table 54 Crystal indication SXA 0 0 Table 48 X-ray protection XPR 0 1 OVERVOLTAGE no overvoltage detected overvoltage detected IVW Table 49 Colour decoder mode (TDA8374 and TDA8375) CD2 0 0 0 0 1 1 1 1 1997 Jul 01 CD1 0 0 1 1 0 0 1 1 CD0 0 1 0 1 0 1 0 1 STANDARD no colour standard identified NTSC with crystal at pin 34 PAL with crystal at pin 35 SECAM NTSC with crystal at pin 35 PAL with crystal at pin 34 spare spare 25 0 1 VIDEO SIGNAL no standard video signal detected standard video signal detected (525 or 625 lines) 1 1 SXB 0 1 0 1 CRYSTAL two 3.6 MHz crystals one 3.6 MHz crystal one 4.4 MHz crystal 3.6 MHz and 4.4 MHz crystals Table 55 Condition vertical divider Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors Table 56 IC version indication ID2 0 0 0 0 1 1 1 1 ID1 0 0 1 1 0 0 1 1 ID0 0 1 0 1 0 1 0 1 STANDARD TDA8373 TDA8377 TDA8374B TDA8374A TDA8374 TDA8377A TDA8375A TDA8375 TDA837x family LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VP Tstg Tamb Tsld Tj Ves PARAMETER supply voltage storage temperature operating ambient temperature soldering temperature operating junction temperature electrostatic handling HBM; all pins; notes 1 and 2 MM; all pins; notes 1 and 3 Notes 1. All pins are protected against ESD by means of internal clamping diodes. 2. Human Body Model (HBM): R = 1.5 k; C = 100 pF. 3. Machine Model (MM): R = 0 ; C = 200 pF. QUALITY SPECIFICATION In accordance with "SNW-FQ-611E". The number of the quality specification can be found in the "Quality Reference Handbook". The handbook can be ordered using the code 9397 750 00192. Latch-up * Itrigger 100 mA or 1.5VP(max) * Itrigger -100 mA or -0.5VP(max). for 5 s CONDITIONS - -25 0 - - -2000 -200 MIN. MAX. 9.0 +150 70 260 150 +2000 +200 V C C C C V V UNIT 1997 Jul 01 26 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family CHARACTERISTICS VP = 8 V; Tamb = 25 C; the pin numbers given refer to the SDIP56 package; unless otherwise specified. SYMBOL Supplies MAIN SUPPLY (PIN 12) VP1 IP1 Ptot VP2 IP2 IF circuit VISION IF AMPLIFIER INPUTS (PINS 48 AND 49) Vi(rms) input sensitivity (RMS value) note 1 fi = 38.90 MHz fi = 45.75 MHz fi = 58.75 MHz Ri Ci Gv Vi(max)(rms) input resistance (differential) input capacitance (differential) voltage gain control range maximum input signal (RMS value) note 2 note 2 - - - - - 64 100 70 70 70 2 3 - 150 100 100 100 - - - - V V V k pF dB mV supply voltage supply current total power dissipation 7.2 - - 7.2 - 8.0 110 900 8.8 - - 8.8 - V mA mW PARAMETER CONDITIONS MIN. TYP. MAX. UNIT HORIZONTAL OSCILLATOR SUPPLY (PIN 37) supply voltage supply current 8.0 6 V mA PLL DEMODULATOR (PLL FILTER ON PIN 5); note 3 fPLL fcr(PLL) tacq(PLL) fVCO(T) ftune(VCO) fDAC fshift(L') PLL frequency range PLL catching range PLL acquisition time VCO frequency variation with temperature VCO tuning range frequency variation per step of the DAC (A0 to A6) frequency shift with the L' FA bit note 4 via the I2C-bus 32 - - - - - - - 2 - tbf 2.5 20 5.5 60 - 20 - - - - MHz MHz ms kHz/K MHz kHz MHz 1997 Jul 01 27 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors SYMBOL PARAMETER CONDITIONS - MIN. TDA837x family TYP. - - MAX. UNIT VIDEO AMPLIFIER OUTPUT (PIN 6); note 5 Vo zero signal output level negative modulation; note 6 negative modulation positive modulation when available 4.7 2.0 2.0 4.5 0 V V V V % positive modulation; note 6 - V6(ts) V6(w) V6 top sync level white level difference in amplitude between negative and positive modulation video output impedance internal bias current of NPN emitter follower output transistor maximum source current bandwidth of demodulated output signal differential gain differential phase video non-linearity white spot clamp level noise inverter threshold clamp level noise inverter insertion level intermodulation blue yellow S/N signal-to-noise ratio note 9 note 9 notes 4 and 10 Vo = 0.92 or 1.1 MHz Vo = 2.66 or 3.3 MHz Vo = 0.92 or 1.1 MHz Vo = 2.66 or 3.3 MHz notes 4 and 11 Vi = 10 mV at end of control range V6(rc) V6(2H) residual carrier signal residual 2nd harmonic of carrier signal note 4 note 4 52 52 - - 60 60 56 60 at -3 dB note 7 notes 4 and 7 note 8 1.9 - - 2.1 - 15 Zo Ibias Isource(max) B Gdiff diff NLvid Vclamp Nth(clamp) Nins - 1.0 - 6 - - - - - - 50 - - 9 2 - - 5.3 1.7 2.6 66 66 62 66 60 61 5.5 2.5 - - 5 - 5 5 5 - - - - - - - - - - - mA mA MHz % deg % V V V dB dB dB dB dB dB mV mV 1997 Jul 01 28 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors SYMBOL PARAMETER CONDITIONS MIN. TDA837x family TYP. MAX. UNIT IF AND TUNER AGC; note 12 Timing of IF-AGC with a 2.2 F capacitor (pin 53) modulated video interference tres(IFinc) response time to an IF input signal amplitude increase of 52 dB response to an IF input signal amplitude decrease of 52 dB allowed leakage current of the AGC capacitor 30% AM for 1 to 100 mV; 0 to 200 Hz (system B/G) positive (when available) and negative modulation negative modulation positive modulation (when available) negative modulation positive modulation (when available) - - - 2 10 - % ms tres(IFdec) - - - - 50 100 - - - - 10 200 ms ms A nA I53 Tuner take-over adjustment (via I2C-bus) Vi(min)(rms) Vi(max)(rms) minimum starting level for tuner take-over (RMS value) maximum starting level for tuner take-over (RMS value) - 40 0.4 80 0.8 - mV mV Tuner control output (pin 54) VoAGC(max) Vo(sat) IoAGC(max) ILI(RF) Vi maximum tuner AGC output voltage output saturation voltage maximum tuner AGC output swing leakage current RF AGC input signal variation for a control current variation of 1 mA maximum tuner gain; note 2 minimum tuner gain; I54 = 2 mA - - 5 - 0.5 - - - - 2 VP + 1 300 - 1 4 V mV mA A dB AFC OUTPUT (VIA I2C-BUS); note 13 RESAFC wsen wsenL AFC resolution window sensitivity window sensitivity in large window mode - 65 195 2 80 240 - 100 300 bits kHz kHz VIDEO IDENTIFICATION OUTPUT (VIA I2C-BUS) td delay time of identification after the AGC has stabilized on a new transmitter - - 10 ms 1997 Jul 01 29 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors SYMBOL Sound circuit DEMODULATOR PART Vi(crPLL)(rms) fcr(PLL) Ri Ci AMR DE-EMPHASIS Vo(rms) Ro VO Vo(rms) VoAVL(rms) VoFAV(rms) Ro VO THD PSRR S/Nint S/Next Tdep(out) CR VCstep OSS Vshift output signal amplitude (RMS value) output resistance DC output voltage at -6 dB; note 14 note 16 note 14 note 14 - - - 500 300 - - - note 17 FAV = 1; note 18 power supply ripple rejection internal signal-to-noise ratio external signal-to-noise ratio temperature dependancy of output level control range step size volume control control curve suppression of output signal when the mute is active DC shift of the output level when the mute is activated - - 80 10 note 4 notes 4 and 19 notes 4 and 19 notes 4 and 20 - - - - - - tbf - input limiting voltage for PLL catching range (RMS value) PLL catching range input resistance input capacitance AM rejection note 14 note 2 note 2 - 4.2 - - 1 - PARAMETER CONDITIONS MIN. TDA837x family TYP. MAX. UNIT 2 6.8 - 5 - - - - 900 500 - - - 0.5 tbf - - - tbf tbf - see Fig.8 - 50 mV MHz k pF dB 8.5 - 66 Vi = 50 mV (RMS); note 15 60 500 15 3 mV k V AUDIO ATTENUATOR CIRCUIT controlled output signal amplitude (RMS value) output signal level when AVL is activated (RMS value) output signal level when FAV is activated (RMS value) output resistance DC output voltage total harmonic distortion 700 400 500 500 3.3 - - tbf 60 80 - 80 1.5 mV mV mV V % % dB dB dB dB dB dB dB mV EXTERNAL AUDIO INPUT Vi(rms) Ri input signal amplitude (RMS value) input resistance - - 500 25 1500 - mV k 1997 Jul 01 30 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors SYMBOL Gv(in-out) ct Gmax Gmin Iatt Idec Vctrl(max) Vctrl(min) PARAMETER voltage gain between input and output crosstalk between audio signals CONDITIONS maximum volume - 60 - - - - maximum boost minimum boost - - MIN. TDA837x family TYP. 12 - 6 -14 1 200 1 5 - - - - - - - - MAX. UNIT dB AUTOMATIC VOLUME LEVELLING CIRCUIT (TDA8373 AND TDA8374 ONLY; CAPACITOR CONNECTED TO PIN 45) gain gain attack charge current decay discharge current control voltage control voltage maximum boost; note 16 minimum boost dB dB mA nA V V CVBS, Y/C, RGB, CD inputs and luminance input and output CVBS AND Y/C SWITCH (PINS 11, 13, 17 AND 38) V11(p-p) I17 SSCVBS V10(p-p) CVBS or Y input voltage (peak-to-peak value) CVBS input current suppression of non-selected CVBS input signal chrominance input voltage (burst amplitude) (peak-to-peak value) output signal amplitude (peak-to-peak value) output impedance top sync level notes 4 and 22 notes 2 and 23 note 21 - - 50 - 1.0 4 - 0.3 1.4 - - 0.45 V A dB V V38(p-p) Zo Vsync V23-25(p-p) - - - note 24 - 1.0 - 2.5 - 250 - 0.8 V V RGB INPUTS (PINS 23, 24 AND 25) input signal amplitude for an output signal of 2 V (black-to-white) (peak-to-peak value) input signal amplitude before clipping occurs (peak-to-peak value) difference between black level of internal and external signals at the outputs input currents delay difference for the three channels note 2 note 4 0.7 V V23-25(p-p) note 4 1.0 - - V Vo - - 20 mV I23-25 td - - 0.1 0 1 - A ns FAST BLANKING (PIN 26) Vi V26(max) input voltage maximum input pulse no data insertion data insertion insertion - 0.9 - - - - 0.3 - 3.0 V V V 1997 Jul 01 31 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors SYMBOL td(blank,RGB) tsw I26 SSint SSext PARAMETER delay difference of blanking and RGB signals switching speed of blanking circuit input current suppression of internal RGB signals suppression of external RGB signals input voltage to insert black level at the RGB outputs to facilitate `On Screen Display' signals being applied to the outputs delay between blanking input and RGB outputs input signal amplitude (R - Y) (peak-to-peak value) input signal amplitude (B - Y) (peak-to-peak value) input current for both inputs insertion; fi = 0 to 5 MHz; notes 4 and 22 no insertion; fi = 0 to 5 MHz; notes 4 and 22 note 4 CONDITIONS - - - - - MIN. - 10 - 55 55 TDA837x family TYP. MAX. 50 - 0.2 - - UNIT ns ns mA dB dB Vi 4 - - V td(blank-RGB) - - 80 ns COLOUR DIFFERENCE INPUT SIGNALS (PINS 31 AND 32) V31(p-p) V32(p-p) I31,32 V27,28 note 2 note 2 note 2 - - - - 1.05 1.35 0.1 - - 1.0 - V V A V LUMINANCE INPUTS AND OUTPUTS (PINS 27 AND 28); note 25 output signal amplitude (black-to-white) 1 Chrominance filters CHROMINANCE TRAP CIRCUIT; note 26 ftrap QF CSR ftrap(SECAM) fc Qbp trap frequency trap quality factor colour subcarrier rejection trap frequency during SECAM reception note 27 - - 20 - - - fosc 2 - 4.3 - - - - - - dB MHz MHz CHROMINANCE BAND-PASS CIRCUIT centre frequency band-pass quality factor 1.1fosc 3 MHz Luminance processing Y DELAY LINE td(Y) Bdel(int) tW delay time bandwidth of internal delay line note 4 note 4 - 8 - 480 - 160 - - - ns MHz PEAKING CONTROL; note 28 width of preshoot or overshoot at 50% of pulse; note 8 ns 1997 Jul 01 32 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors SYMBOL Sc(th) OS neg/pos PARAMETER peaking signal compression threshold overshoot at maximum peaking ratio of negative and positive overshoots peaking control curve NOISE CORING STAGE S coring range - 15 at 100% of peak white at 50% of peak white at 15% of peak white Horizontal and vertical synchronization and drive circuits SYNC VIDEO INPUT (PINS 11, 13 AND 17) V11,13,17 SLHS SLVS ffr ffr f/VP f(max)(T) sync pulse amplitude slicing level for horizontal sync slicing level for vertical sync note 2 note 30 note 30 50 - - - - VP = 8.0 V 10%; note 4 Tamb = 0 to 70 C; note 4 - - -1 -1 6 15 16 steps positive negative CONDITIONS - - - - MIN. TDA837x family TYP. 50 45 80 1.8 see Fig.9 - - - - - MAX. UNIT IRE % % IRE BLACK LEVEL STRETCHER; note 29 BLshift(max) BLshift maximum black level shift level shift 21 0 - 8 27 +1 +3 10 IRE IRE IRE IRE 300 50 30 350 - - - 2 0.5 80 mV % % HORIZONTAL OSCILLATOR free running frequency spread on free running frequency frequency variation with respect to the supply voltage maximum frequency variation with temperature 15625 - 0.2 - Hz % % Hz FIRST CONTROL LOOP (FILTER CONNECTED TO PIN 43); note 31 fhr(PLL) fcr(PLL) S/N holding range PLL catching range PLL signal-to-noise ratio of the video input signal at which the time constant is switched hysteresis at the switching point note 4 - 0.6 - 0.9 0.9 20 1.2 - - kHz kHz dB HYS i/o tcr - - 11 1 - - - dB s/s s SECOND CONTROL LOOP (CAPACITOR CONNECTED TO PIN 42) control sensitivity control range from start of horizontal output to flyback at nominal shift position horizontal shift range 63 steps 150 12 tshift 2 - - s 1997 Jul 01 33 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors SYMBOL Vprot Ii(prot) VOL Io(max) Vo(max) fsw tsw PARAMETER control sensitivity for dynamic phase compensation voltage to switch-on the flash protection input current during protection note 32 CONDITIONS - 6 - Io = 10 mA - 10 - note 4 Vo = HIGH frequency during switch-on and switch-off switch-on time maximum RGB drive minimum RGB drive FLYBACK PULSE INPUT AND SANDCASTLE OUTPUT (PIN 41) Ii(fb) V41 Vi(clamp) tW td(bk-sync) required input current during the note 4 flyback pulse output voltage clamped input voltage during flyback pulse width delay of start of burst key to start of sync burst key pulse vertical blanking; note 34 during burst key during blanking 100 4.8 1.8 2.6 3.3 - 5.2 - - - - - - - MIN. TDA837x family TYP. 5.3 - - - - - 50 75 2fH 50 100 50 - - 1 MAX. UNIT s/V V mA HORIZONTAL OUTPUT (PIN 40); note 33 LOW level output voltage maximum allowed output current maximum allowed output voltage duty factor 0.3 - VP - - - - - - 300 5.8 2.2 3.4 3.7 - 5.6 V mA V % % Hz ms ms ms A V V V s lines s 5.3 2.0 3.0 3.5 14 5.4 VERTICAL OSCILLATOR; TDA8373 AND TDA8377 OPERATING AT 60 HZ; note 35 ffr flock LR free running frequency frequency locking range divider value not locked locking range - 45 - 488 50/60 - 625/525 - - 64.5 - 722 Hz Hz lines lines/ frame VERTICAL RAMP GENERATOR (PINS 51 AND 52) V51(p-p) Idch Ich Vslope 1997 Jul 01 sawtooth amplitude (peak-to-peak value) discharge current charge current set by external resistor vertical slope note 36 control range (63 steps) 34 VS = 1FH; C = 100 nF; R = 39 k - - - -20 3.5 1 19 - - - - +20 V mA A % Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors SYMBOL Ich VrampL PARAMETER charge current increase LOW voltage level of ramp in the normal or expand mode CONDITIONS f = 60 Hz - - MIN. TDA837x family TYP. 20 2.07 - - MAX. UNIT % V VERTICAL DRIVE OUTPUTS (PINS 46 AND 47) Io(dif)(p-p) ICM V46,47 V50 mscan vsen EWsen Ieq V50 DE-INTERLACE ffd CR Ieq VoEW IoEW CR Ieq CR Ieq CR Ieq CR Ieq(dif)(p-p) first field delay - 63 steps 100 0 1.0 0 0.5H - - - - - - - - - - - - - 65 700 8.0 1200 % A V A % A % A % A % A differential output current (peak-to-peak value) common mode current output voltage range VA = 1FH - - 0 0.95 400 - - - 6.3 -6.3 - 3.9 - - 4.0 mA A V EHT TRACKING/OVERVOLTAGE PROTECTION (PIN 50) input voltage range scan modulation range vertical sensitivity E-W sensitivity E-W equivalent output current overvoltage detection level note 32 when switched on 1.2 -5 - - +100 - 2.8 +5 - - -100 - V % %/V %/V A V E-W WIDTH (TDA8375A, TDA8377A, TDA8375 AND TDA8377); note 37 control range equivalent E-W output current E-W output voltage range E-W output current range E-W PARABOLA/WIDTH (TDA8375A, TDA8377A, TDA8375 AND TDA8377) control range equivalent E-W output current 63 steps E-W = 3FH 0 0 -43 -190 -5 -100 63 steps; SC = 00H SC = 00H 80 760 22 440 E-W CORNER/PARABOLA (TDA8375A, TDA8377A, TDA8375 AND TDA8377) control range equivalent E-W output current 63 steps PW = 3FH; E-W = 3FH 0 0 E-W TRAPEZIUM (TDA8375A, TDA8377A, TDA8375 AND TDA8377) control range equivalent E-W output current 63 steps +5 +100 VERTICAL AMPLITUDE control range equivalent differential vertical drive output current (peak-to-peak value) 120 1140 VERTICAL SHIFT CR Ieq(dif) control range equivalent differential vertical drive output current 35 63 steps -5 -50 - - +5 +50 % A 1997 Jul 01 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors SYMBOL S-CORRECTION CR control range 63 steps 0 - PARAMETER CONDITIONS MIN. TDA837x family TYP. MAX. UNIT 30 % VERTICAL EXPAND (ZOOM) MODE (TDA8375 AND TDA8377); note 38 Output current variation compared with nominal scan Io Io(lim) vertical expand factor output current limiting and RGB blanking 0.75 1.08 1.38 A A Colour demodulation part CHROMINANCE AMPLIFIER CRACC VACC ACC control range change in amplitude of the output signals over the ACC range threshold colour killer ON hysteresis colour killer OFF note 39 26 - - - - 2 dB dB thon hysoff -30 at strong signal conditions; - S/N 40 dB; note 4 at noisy input signals; note 4 - - +3 +1 - - - dB dB dB ACL CIRCUIT; note 40 chrominance burst ratio at which the ACL starts to operate REFERENCE PART - 3.0 - Phase-locked loop; note 41 fcr frequency catching range phase shift for a 400 Hz deviation of the oscillator frequency note 4 360 - 600 - - 2 Hz deg Oscillator TCosc fosc Rneg(min) CL(max) HUE CONTROL CRhue hue control range hue control curve 63 steps 35 40 - deg see Fig.10 temperature coefficient of the oscillator frequency oscillator frequency deviation with respect to the supply minimum negative resistance maximum load capacitance note 4 VP = 8 V 10%; note 4 - - - - 2.0 - - - 2.5 250 1 15 Hz/K Hz k pF 1997 Jul 01 36 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors SYMBOL hue hue(T) V30(p-p) V29(p-p) G PARAMETER hue variation for 10% VP hue variation with temperature (R - Y) output signal amplitude (peak-to-peak value) (B - Y) output signal amplitude (peak-to-peak value) gain ratio between both demodulators G(B - Y) and G(R - Y) spread of signal amplitude ratio PAL/NTSC output impedance between (R - Y) and (B - Y) bandwidth of demodulators residual carrier output (peak-to-peak value) TDA8374 and TDA8375; note 4 note 2 -3 dB; note 43 fc; (R - Y) output fc; (B - Y) output 2fc; (R - Y) output 2fc; (B - Y) output V30(p-p) Vo(T) Vo/VP E H/2 ripple at (R - Y) output (peak-to-peak value) change of output signal amplitude with temperature change of output signal amplitude with supply voltage phase error in the demodulated signals note 4 note 4 note 4 - - - - - - - - - note 4 Tamb = 0 to 70 C; note 4 TDA8374 and TDA8375; note 42 TDA8374 and TDA8375; note 42 CONDITIONS - - - - 1.60 MIN. 0 0 TDA837x family TYP. - - - - MAX. UNIT deg deg DEMODULATORS (PINS 29 AND 30) 0.525 0.675 1.78 V V 1.96 V Zo B V29,30(p-p) -1 - - - 500 650 +1 - - 5 5 5 5 25 - 0.1 5 dB kHz mV mV mV mV mV %/K dB deg 0.1 - - COLOUR DIFFERENCE MATRICES (IN CONTROL CIRCUIT) TDA8374 AND TDA8375 PAL or (SECAM when TDA8395 is applied); (R - Y) and (B - Y) not affected (G - Y)/ (R - Y) (G - Y)/ (B - Y) (B - Y) (R - Y) (G - Y) ratio of demodulated signals ratio of demodulated signals - - -0.51 10% -0.19 25% - - NTSC mode; the colour-difference matrix results in the following signals (nominal hue setting) (B - Y) signal 2.03/0 (R - Y) signal 1.59/95 (G - Y) signal 0.61/240 2.03UR -0.14UR + 1.58VR -0.31UR - 0.53VR 1997 Jul 01 37 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors SYMBOL PARAMETER CONDITIONS MIN. TDA837x family TYP. MAX. UNIT COLOUR DIFFERENCE MATRICES (IN CONTROL CIRCUIT) TDA8373 AND TDA8377 MAT = 0; the colour-difference matrix results in the following signals (nominal hue setting) (B - Y) (R - Y) (G - Y) (B - Y) (R - Y) (G - Y) fref V33(p-p) (B - Y) signal 2.03/0 (R - Y) signal 1.59/95 (G - Y) signal 0.61/240 (B - Y) signal 1.14/-10 (R - Y) signal 1.14/100 (G - Y) signal 0.30/235 reference frequency output signal amplitude (peak-to-peak value) 2.03UR -0.14UR + 1.58VR -0.31UR - 0.53VR 1.12UR - 0.20VR -0.20UR + 1.12VR -0.17UR - 0.25VR - 0.2 3.58 or 4.43 0.25 - 0.3 MHz V MAT = 1; the colour-difference matrix results in the following signals (nominal hue setting) REFERENCE SIGNAL OUTPUT (PIN 33); note 44 COMMUNICATION WITH THE TDA8395 (TDA8374 AND TDA8375 ONLY) Vo output level PAL/NTSC identified no PAL/NTSC identified; SECAM (by TDA8395) identified I31 required current to stop PAL/NTSC identification circuit during SECAM - - 1.5 5.0 - - V V 150 - - A Control part SATURATION CONTROL; note 24 (SEE Fig.11) CRsat CRcon saturation control range 63 steps 52 - - - 15 - - - 0.5 dB CONTRAST CONTROL; note 24 (SEE Fig.12) contrast control range tracking between the three channels over a control range of 10 dB BRIGHTNESS CONTROL (SEE Fig.13) CRbri V19-21(p-p) brightness control range 63 steps - 1.8 0.7 2.1 - 2.4 V 63 steps dB dB RGB OUTPUT SIGNALS (PINS 19 TO 21) output signal amplitude at note 24 nominal luminance input signal, nominal contrast and white point adjustment (peak-to-peak value) output signal at maximum white point setting (peak-to-peak value) V Vo(max)(p-p) - 3.0 - V 1997 Jul 01 38 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors SYMBOL VBW(max)(p-p) VWP(max)(p-p) PARAMETER maximum signal amplitude (black-to-white) maximum signal amplitude at maximum white point setting (peak-to-peak value) output signal amplitude for the `red' channel at nominal settings for contrast and saturation control and no luminance signal to the input (R - Y, PAL) (peak-to-peak value) difference between blanking level measuring pulse width of the video blanking pulse TDA8375, TDA8377, when the HBL bit is active TDA8375A and TDA8377A; note 46 internal bias current of NPN emitter follower output transistor available output current output impedance control range of the black current stabilization CONDITIONS note 45 - - MIN. TDA837x family TYP. 2.6 3.6 - - MAX. UNIT V V Vred(p-p) tbf 2.1 tbf V Vblank tW(blank) 0.7 14.4 0.8 14.7 0.9 15.0 V s Ibias Io Zo CRbl - - - at Vbl = 2.5 V and nominal - brightness and white-point adjustment (with respect to the measuring pulse) note 4 - - note 4 note 4 - 1.5 5 150 - - - - 1 mA mA V Vbl Vo(4L) bl(T) bl black level shift with picture content output voltage of the 4-L pulse after switch-on variation of black level with temperature relative variation in black level between the three channels during variations of supply voltage (10%) saturation (50 dB) contrast (15 dB) brightness (0.5 V) temperature (range 40 C) - 4.2 1.0 20 - - mV V mV/K nominal controls nominal contrast nominal saturation nominal controls RGB input; note 47 CVBS input; note 47 at fosc at 2fosc plus higher harmonics in RGB outputs - - - - - 60 50 - - - - - - - - - - - 20 20 20 20 20 - - 15 15 mV mV mV mV mV dB dB mV mV S/N Vr(p-p) signal-to-noise ratio of the output signals residual voltage at the RGB outputs (peak-to-peak value) 1997 Jul 01 39 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors SYMBOL B PARAMETER bandwidth of output signals CONDITIONS RGB input at -3 dB CVBS input at -3 dB; fosc = 3.6 MHz CVBS input at -3 dB; fosc = 4.44 MHz S-VHS input; at -3 dB WHITE-POINT ADJUSTMENT I2C-bus setting for nominal gain Ginc(max) Gdec(max) Ibias IL Iscan(max) Zi VCR VdifCR VBR VdifBR Vbias Zint Vdet Ii(min) Ii(max) Notes 1. On set AGC. maximum increase of the gain maximum decrease of the gain HEX code HEX code 3FH HEX code 00H - 40 35 8 - - 5 MIN. - TDA837x family TYP. - - - - - 2.8 3.5 - 20H 50 45 MAX. UNIT MHz MHz MHz MHz 60 55 - - - - - - - - - - - - - % % A A mA k BLACK CURRENT STABILIZATION (PIN 18); note 48 bias current for the picture tube cathode acceptable leakage current maximum current during scan input impedance nominal white point setting - - - - - - - - - - - - - 10 100 0.3 15 BEAM CURRENT LIMITING/VERTICAL GUARD INPUT (PIN 22); note 49 contrast reduction starting voltage voltage difference for full contrast reduction brightness reduction starting voltage voltage difference for full brightness reduction internal bias voltage internal impedance detection level for vertical guard minimum input current to activate the guard circuit maximum allowable input current 3.1 2 1.6 1 3.3 40 3.65 100 1 V V V V V k V A mA 2. This parameter is not tested during production and is just given as application information for the designer of the television receiver. 3. Loop bandwidth BL = 60 kHz (natural frequency fn = 15 kHz; damping factor d = 2; calculated with sync level as FPLL input signal level). LC-VCO circuit: Q0 60, Cext = 12 pF, Cint = 20 pF. 4. This parameter is not tested during production but is guaranteed by the design and qualified by means of matrix batches which are made in the pilot production period. 5. Measured at 10 mV (RMS) top sync input signal. 6. So called projected zero point, i.e. with switched demodulator. 1997 Jul 01 40 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family 7. Measured in accordance with the test line given in Fig.14. For the differential phase test the peak white setting is reduced to 87%. a) The differential gain is expressed as a percentage of the difference in peak amplitudes between the largest and smallest value relative to the subcarrier amplitude at blanking level. b) The phase difference is defined as the difference in degrees between the largest and smallest phase angle. 8. This figure is valid for the complete video signal amplitude (peak white-to-black), see Fig.15. 9. The noise inverter is only active in the `strong signal mode' (no noise detected in the incoming signal). 10. The test set-up and input conditions are given in Fig.16. The figures are measured with an input signal of 10 mV (RMS). V O(b-w) 11. Measured with a source impedance of 75 , where: S/N = 20 log -------------------------------------------------------V m ( rms ) ( B = 5 MHz ) 12. The AGC response time is also dependent on the acquisition time of the PLL demodulator. The values given are valid when the PLL is in lock. 13. The AFC control voltage is obtained from the control voltage of the VCO of the PLL demodulator. The tuning information is supplied to the tuning system via the I2C-bus. Two bits are reserved for this function. The AFC value is valid only when the SL bit = 1. 14. Vi = 100 mV (RMS), FM: 1 kHz, f = 50 kHz. 15. Vi = 50 mV (RMS), f = 4.5 to 5.5 MHz; FM: 70 Hz, 50 kHz deviation; AM: 1 kHz, 30% modulation. 16. The Automatic Volume Levelling (AVL) circuit automatically stabilizes the audio output signal to a certain level which can be set by means of the volume control. This AVL function prevents big audio output fluctuations due to variation of the modulation depth of the transmitter. The AVL can be switched on and off via the I2C-bus. For the TDA8373 the AVL is active over an input voltage range (measured at the de-emphasis output) between 75 and 750 mV (RMS). For the TDA8374 this input level is dependent on the crystals which are connected to the colour decoder. When only 3.5 MHz crystals are connected (indicated via the XA/XB bits) the active input level is identical to that of the TDA8373. When a 4.4 MHz crystal is connected the input signal range is increased to 150 to 1500 mV (RMS), this to cope with the larger FM swing of European transmitters. The AVL control curve for the 2 standards is given in Fig.29 and Fig.30. The control range of +6 to -14 dB is valid for input signals with 50% of the maximum frequency deviation. 17. Vi = 100 mV (RMS), f = 5.5 MHz; FM: 1 kHz, 17.5 kHz deviation, 15 kHz bandwidth; audio attenuator at -6 dB. 18. Vi = 100 mV (RMS), f = 4.5 to 5.5 MHz, FM: 1 kHz, 100 kHz deviation. 19. Unweighted RMS value, Vi = 100 mV (RMS), FM: 1 kHz, 50 kHz deviation, volume control: -6 dB. 20. Audio attenuator at -20 dB; temperature range = 10 to 50 C. 21. Signal with negative-going sync. Amplitude includes sync pulse amplitude. 22. This parameter is measured at nominal settings of the various controls. 23. Indicated as a signal for a colour bar with 75% saturation (chroma-to-burst ratio = 2.2 : 1). 24. Nominal contrast is specified with the DAC in position 20H. Nominal saturation as maximum -10 dB. At nominal settings of brightness and white point the black level at the outputs is 300 mV lower than the level of the black current measuring pulses. 25. The luminance output and input of the TDA8375A, TDA8377A, TDA8375 and TDA8377 can be connected directly. When additional picture improvement ICs (such as the TDA9170) are applied the inputs of these ICs must be AC-coupled because of the black level clamp requirement. The output of the picture improvement ICs can be directly coupled to the luminance input as long as the DC level of the signal has a value between 1 and 7 V. To be able to apply CTI ICs such as the TDA4565 and TDA4566 the gain of the luminance channel can be increased via the setting of the GAI bit in the I2C-bus subaddress 03. 1997 Jul 01 41 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family 26. When the colour decoder is forced to a fixed subcarrier frequency (via the XA/XB or the CM bits) the chroma trap is always switched on, also when no colour signal is identified. When 2 crystals are active the chroma trap is switched off when no colour signal is identified. 27. The -3 dB bandwidth of the circuit can be calculated using the following equation: 1 f -3 dB = f osc 1 - ------- 2Q 28. Valid for a signal amplitude on the Y input of 0.7 V (black-to-white) (100 IRE) with a rise time (10% to 90%) of 70 ns and the video switch in the Y/C mode. During production the peaking function is not tested by measuring the overshoots but by measuring the frequency response of the Y output. 29. For video signals with a black level which deviates from the back porch blanking level the signal is `stretched' to the blanking level. The amount of correction depends on the IRE value of the signal (see Fig.17). The black level is detected by means of an external capacitor. The black level stretcher can be made inoperative by connecting the pin to ground. The values given are valid only when the luminance input signal has an amplitude of 1 V (p-p). 30. The slicing level is independent of sync pulse amplitude. The given percentage is the distance between the slicing level and the black level (back porch). When the amplitude of the sync pulse exceeds the value of 350 mV the sync separator will slice the sync pulse at a level of 175 mV above top sync. The maximum sync pulse amplitude is 4 V (p-p). 31. To obtain a good performance for both weak signal and VCR playback the time constant of the first control loop is switched depending on the input signal condition and the condition of the bus. Therefore the circuit contains a noise detector and the time constant is switched to `slow' when too much noise is present in the signal. In the `fast' mode, during the vertical retrace time, the phase detector current is increased by 50% so that phase errors due to the head switching of the VCR are corrected as soon as possible. Switching between the two modes can be made automatically or overruled by the bus (see Tables 4, 6, 8 and 10). The circuit contains a video identification circuit which is independent of first loop. This identification circuit can be used to close or open the first control loop when a video signal is present or not on the input. This ensures a stable On-Screen-Display (OSD) when just noise is present at the input. The coupling of the video identification circuit with the first loop can be overruled via the I2C-bus. The coupling between the phase 1 detector and the video identification circuit is only active for `internal' CVBS signals. To prevent the horizontal synchronization being disturbed by anti-copy guard signals, such as Macrovision, the phase detector is gated during the vertical retrace period so that pulses during scan have no effect on the output voltage. The width of the gate pulse is approximately 22 s. Furthermore the phase detector is gated during the lower part of the picture (pulse width = 12 s) to prevent disturbances due to overmodulated subtitles. The latter gating is active only with standard signals (number of lines per frame 625 or 525). During weak signal conditions (noise detector active) the gating is active during the complete scan period and the width of the gate pulse is reduced to 5.7 s so that the effect of the noise is reduced to a minimum. The output current of the phase detector in the various conditions are given in Table 57. 32. The ICs have 2 protection inputs. The protection at pin 42 is intended to be used as `flash' protection. When this protection is activated the horizontal drive is switched off immediately and then switched on again via the slow start procedure. The protection on pin 50 is intended for overvoltage (X-ray) protection. When this protection is activated the horizontal drive can be switched off directly (via the slow stop procedure). It is also possible to continue the horizontal drive and to set the protection bit (XPR) in the output bytes of the I2C-bus. The choice between the 2 modes of operation is made with the PRD bit. 1997 Jul 01 42 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family 33. During switch-on the horizontal output starts with twice the frequency and with a duty cycle of 75% (Vo = HIGH). After approximately 50 ms the frequency is changed to the normal value. Because of the high frequency the peak currents in the horizontal output transistor are limited. Also during switch-off the frequency is switched to twice the value and the RGB drive is set to maximum so that the EHT capacitor is discharged. This switching to maximum drive occurs only when RBL = 0, for RBL = 1 the drive voltage remains minimum during switch-off. After approximately 100 ms the RGB drive is set to minimum and 50 ms later the horizontal drive is switched off. The horizontal output is gated with the flyback pulse so that the horizontal output transistor cannot be switched on during the flyback time. 34. The vertical blanking pulse in the RGB outputs has a width of 26 or 21 lines (50 or 60 Hz system). The width of the vertical sync pulse in the sandcastle pulse has a width of 14 lines. This to prevent a phase distortion on top of the picture due to timing modulation of the incoming flyback pulse. 35. The timing pulses for the vertical ramp generator are obtained from the horizontal oscillator via a divider circuit. This divider circuit has 3 modes of operation. A brief explanation is given below. For the TDA8373 and TDA8377 only the 60 Hz figures are valid. a) Search mode `large window': This mode is switched on when the circuit is not synchronized or when a non-standard signal (number of lines per frame in the 50 Hz mode is between 311 and 314 and in the 60 Hz mode between 261 and 264) is received. In the search mode the divider can be triggered between line 244 and line 361 (approximately 45 to 64.5 Hz). b) Standard mode `narrow window': This mode is switched on when more than 15 succeeding vertical sync pulses are detected in the narrow window. When the circuit is in the standard mode and a vertical sync pulse is missing the retrace of the vertical ramp generator is started at the end of the window. Consequently, the disturbance of the picture is very small. The circuit will switch back to the search window when, for 6 successive vertical periods, no sync pulses are found within the window. c) Standard TV-norm (divider ratio 525 (60 Hz) or 625 (50 Hz): When the system is switched to the narrow window it is checked whether the incoming vertical sync pulses are in accordance with the TV-norm. When 15 standard TV-norm pulses are counted the divider system is switched to the standard divider ratio mode. In this mode the divider is always reset at the standard value even if the vertical sync pulse is missing. When 3 vertical sync pulses are missed the system switches back to the narrow window and when also in this window no sync pulses are found (condition 3 missing pulses) the system switches over to the search window. The vertical divider needs some waiting time during channel-switching of the tuner. When a fast reaction of the divider is required during channel-switching the system can be forced to the search window by means of the NCIN bit in subaddress 08. 36. Conditions: frequency is 60 Hz; normal mode; VS = 1F. 37. The output range percentages mentioned for E-W control parameters are based on the assumption that 400 A variation in E-W output current is equivalent to 20% variation in picture width. Because of the horizontal and vertical zoom feature in the TDA8375 and TDA8377 (see also note 38) the E-W width control range is increased compared with previous ICs such as the TDA8366. The increased E-W width control is also available in the TDA8375A and TDA8377A although these devices do not have the vertical zoom feature. 38. The TDA8375 and TDA8377 have a zoom adjustment possibility for the vertical and horizontal deflection. For this reason an extra DAC has been added in the vertical amplitude control which controls the vertical scan amplitude between 0.75 and 1.38 of the nominal scan. At an amplitude of 1.08 of the nominal scan the output current is limited and the blanking of the RGB outputs is activated (see Fig.28). In addition to the variation of the vertical amplitude the vertical slope control range is also increased. This gives the possibility to vary the position of the bottom part of the picture independent from the upper part. The nominal scan height must be adjusted at a position of 19H of the vertical `zoom' DAC 1997 Jul 01 43 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family 39. At a chrominance input voltage of 660 mV (p-p) [colour bar with 75% saturation i.e. burst signal amplitude 300 mV (p-p)] the dynamic range of the ACC is +6 and -20 dB. 40. The ACL function is available in the NTSC devices and is active in the PAL/NTSC devices when NTSC signals are received. The ACL circuit reduces the gain of the chroma amplifier for input signals with a chroma-to-burst ratio which exceeds a value of 3.0. 41. All frequency variations are referenced to 3.58 or 4.43 MHz carrier frequency. All oscillator specifications are measured with the Philips crystal series 9922 520 with a series capacitor of 18 pF. The oscillator circuit is rather insensitive to the spurious responses of the crystal. As long as the resonance resistance of the 3rd overtone is higher than that of the fundamental frequency the oscillator will operate at the correct frequency. Typical parameters for the above mentioned crystals are as follows: a) Load resonance frequency f0 = 4.433619 or 3.579545 MHz (CL = 20 pF). b) Motional capacitance Cmot = 20.6 fF (4.43 MHz crystal) or 14.7 fF (3.58 MHz crystal). c) Parallel capacitance Cpar = 5 pF for both crystals. The minimum detuning range can only be specified if both the IC and the crystal tolerances are known and the figures given are therefore valid for the specified crystal series. In this figure tolerances of the crystal with respect to nominal frequency, motional capacitance and ageing have been taken into account and have been counted for gaussian addition. Whenever different typical crystal parameters are used the following equation might be helpful for calculating the impact on the detuning capabilities: C mot The detuning range divided by ----------------------------- C par 2 1 + ---------- CL The resulting detuning range should be corrected for temperature shift and supply deviation of both the IC and the crystal. The actual series capacitance in the application should be CL = 18 pF to account for parasitic capacitances on and off chip. For 3-norma applications with 2 crystals connected to one pin the maximum parasitic capacitance of the crystal pin should not exceed 15 pF. 42. The (R - Y) and (B - Y) signals are demodulated with a phase difference of the reference carrier of 90 and a gain ( B - Y) ratio -------------------- = 1.78. ( R - Y) The output signal amplitudes of the TDA8373 and TDA8377A have twice the value. This is necessary to compensate for the gain of the baseband delay line (TDA4665). The matrixing to the required signals is realized in the control part. 43. This parameter indicates the bandwidth of the complete chrominance circuit including the chrominance band-pass filter. The bandwidth of the low-pass filter of the demodulator is approximately 1 MHz. 44. The sub-carrier output signal can be used as reference signal of external comb filter ICs (all ICs) and as a reference signal for the SECAM decoder TDA8395 (only TDA8374 and TDA8375). In the latter types the output signal is continuously available when PAL or NTSC signals are detected. When the system identifies a SECAM signal the reference signal is only present in the vertical retrace period. This to prevent interference between the reference signal and the SECAM input signal. For comb filter applications the DC load on this pin should be limited to 50 A to avoid problems with SECAM identification. 45. At nominal setting of the gain control. When this amplitude is exceeded the signal will be clipped. 46. When the reproduction of 4 : 3 pictures on a 16 : 9 picture tube is realized by means of a reduction of the horizontal scan amplitude, the edges of the picture may be slightly disturbed. This effect can be prevented by adding additional blanking to the RGB signals. This blanking pulse is derived from the horizontal oscillator and is directly related to the incoming video signal (independent of the flyback pulse). The additional blanking overlaps the normal blanking signal with approximately 1 s on both sides. This blanking is activated with the HBL bit (only in the TDA8375 and TDA8377). 47. Signal-to-noise ratio (S/N) is specified as a peak-to-peak signal with respect to RMS noise (bandwidth 5 MHz). 1997 Jul 01 44 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family 48. This is a current input. The indicated value of the nominal bias current is obtained at the nominal setting of the gain (white point) control. The actual value of the bias current depends on the gain control setting of each channel. As a result the `black current' of each gun is adapted to the white point setting so that the background colour will follow the white point adjustment. 49. The beam current limiting and the vertical guard function have been combined on this pin. The beam current limiting function is active during the vertical scan period. Table 57 Output current of the phase detector in the various conditions I2C-BUS COMMANDS VID - - - - - - - - 0 - Note 1. During vertical retrace the width is 22 s and during the lower part of the picture 12 s. In the other conditions the width is 5.7 s and the gating is continuous. POC 0 0 0 0 0 0 0 - 0 1 FOA 0 0 0 0 0 1 1 1 - - FOB 0 0 0 1 1 0 0 1 - - IC CONDITIONS IDENT yes yes yes yes yes yes yes - no - COIN yes yes no yes no yes yes - - - NOISE no yes - - - no yes - - - SCAN 180 30 180 30 180 180 30 180 6 - -1 CURRENT/MODE V-RETR 270 30 270 30 270 270 30 270 6 - GATING yes(1) yes no yes no yes yes no no - MODE auto auto auto slow slow fast slow fast OSD off handbook, halfpage MGK290 handbook, halfpage MGK291 0 (dB) -20 -40 40 (%) 30 20 -60 -80 -100 10 0 0 10 20 30 DAC (HEX) 40 0 4 8 C F 10 DAC (HEX) Positive overshoot. Fig.8 Volume control curve. Fig.9 Peaking control curve. 1997 Jul 01 45 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family handbook, halfpage MGK292 handbook, halfpage MGK293 (deg) 40 300 (%) 250 200 150 100 50 0 0 10 20 30 DAC (HEX) 40 0 10 20 30 DAC (HEX) 40 20 0 -20 -40 Fig.10 Hue control curve. Fig.11 Saturation control curve. handbook, halfpage MGK294 handbook, halfpage MGK295 100 (%) 80 0.7 (V) 0.35 60 0 40 -0.35 20 -0.7 0 0 10 20 30 DAC (HEX) 40 0 10 20 30 DAC (HEX) 40 Relative variation with respect to the measuring pulse. Fig.12 Contrast control curve. Fig.13 Brightness control curve. 1997 Jul 01 46 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family MBC212 16 % 100% 92% 30% for negative modulation 100% = 10% rest carrier Fig.14 Video output signal. handbook, full pagewidth MBC211 100% 86% 72% 58% 44% 30% 10 12 22 26 32 36 40 44 48 52 56 60 64 s Fig.15 Test signal waveform. 1997 Jul 01 47 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family handbook, full pagewidth 3.2 dB 10 dB 13.2 dB 30 dB 13.2 dB 30 dB SC CC BLUE PC SC CC YELLOW PC MBC213 PC SC ATTENUATOR TEST CIRCUIT SPECTRUM ANALYZER CC gain setting adjusted for blue MBC210 Input signal conditions: SC = Sound Carrier; CC = Colour Carrier; PC = Picture Carrier. All amplitudes with respect to top sync level. V O at 3.58 or 4.4 MHz Value at 0.92 or 1.1 MHz = 20 log ----------------------------------------------------------- + 3.6 dB V O at 0.92 or 1.1 MHz V O at 3.58 or 4.4 MHz Value at 2.66 or 3.3 MHz = 20 log ----------------------------------------------------------V O at 2.66 or 3.3 MHz Fig.16 Test set-up intermodulation. 1997 Jul 01 48 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors MGK297 TDA837x family handbook, halfpage 100 out (IRE) 80 60 40 20 B AB A 0 20 40 60 80 100 in (IRE) 0 -20 A-A = maximum black level shift; B-B = level shift at 15% of peak white. Fig.17 Input/output relationship of the black level stretcher. TEST AND APPLICATION INFORMATION handbook, full pagewidth BANDPASS from tuner SAW FILTER 58 59 4 3 16 10 11 27 17 18 35 36 37 38 33 32 31 TRAP 24 29 21 20 54 50 4.4 MHz 51 3.5 MHz 30 TDA837x 34 62 63 64 56 46 45 39 47 48 57 TDA8395 TDA4665 MGK302 Fig.18 Simplified application diagram. 1997 Jul 01 49 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors East-West output stage TDA837x family In order to obtain correct tracking of the vertical and horizontal EHT correction, the E-W output stage should be dimensioned as illustrated in Fig.19. Resistor Rew determines the gain of the E-W output stage. Resistor Rc determines the reference current for both the vertical sawtooth generator and the geometry processor. The preferred value of Rc is 39 k which results in a reference current of 100 A (Vref = 3.9 V). V scan The value of Rew must be: R ew = R c x ---------------------18 x V ref Example: With Vref = 3.9 V; Rc = 39 k and Vscan = 120 V then Rew 68 k. handbook, full pagewidth Vsupply HORIZONTAL DEFLECTION STAGE Rew Vscan TDA8375 TDA8377 45 52 Rc 39 k (2%) Vref 51 E-W drive E-W OUTPUT STAGE DIODE MODULATOR VEW Csaw 100 nF (5%) MGK300 Fig.19 East-West output stage. Control ranges of geometry control parameters Typical case curves; Rc = 39 k, CSAW = 100 nF. Figures 20 to 23 are valid for all types. Figures 24 to 27 are valid for TDA8375 and TDA8377. 1997 Jul 01 50 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family MGH366 MGH367 handbook, halfpage 600 Ivert (A) 400 handbook, halfpage I 500 vert (A) 300 200 100 0 -100 -300 -500 -700 time t 0 -200 -400 -600 0 1/2 t 1/2 t time t VA = 0, 31H and 63H; VSH = 31H; SC = 0. VS = 0, 31H and 63H; VA = 31H; VHS = 31H; SC = 0. Fig.20 Control range of vertical amplitude. Fig.21 Control range of vertical slope. handbook, halfpage I 600 vert (A) 400 MGH368 handbook, halfpage I 600 vert (A) 400 MGH369 200 200 0 0 -200 -400 -600 0 -200 -400 -600 time t 0 1/2 t 1/2 t time t VSH = 0, 31H and 63H; VA = 31H; SC = 0. SC = 0, 31H and 63H; VA = 31H; VHS = 31H. Picture height does not change with S-correction for nominal vertical amplitude (VA = 31). Fig.22 Control range of vertical shift. Fig.23 Control range of S-correction. 1997 Jul 01 51 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family handbook, halfpage I 1200 ew (A) 1000 MBK039 handbook, halfpage I 900 ew (A) 800 MBK040 800 700 600 600 400 500 200 400 0 0 300 1/2 t time t 0 1/2 t time t EW = 0, 31H and 63H; PW = 31H; CP = 31H. PW = 0, 31H and 63H; EW = 31H; CP = 31H. Fig.24 Control range of E-W width. Fig.25 Control range of E-W parabola/width ratio. MBK041 handbook, halfpage I 900 ew (A) 800 handbook, halfpage 700 MBK042 Iew (A) 600 700 600 500 500 400 400 300 0 1/2 t 300 time t 0 1/2 t time t CP = 0, 31H and 63H; EW = 31H; PW = 63H. TC = 0, 31H and 63H; EW = 31H; PW = 31H; CP = 0. Fig.26 Control range of E-W corner/parabola ratio. Fig.27 Control range of E-W trapezium correction. 1997 Jul 01 52 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors Adjustment of geometry control parameters The deflection processor of the TDA8373 and TDA8374 offers 5 control parameters for picture alignment: * Vertical picture alignment - S-correction - vertical amplitude - vertical slope - vertical shift - Horizontal shift alignment. The TDA8375, TDA8377, TDA8375A and TDA8377A offer in addition the following functions for horizontal alignment: * E-W width * E-W parabola/width * E-W corner/parabola * E-W trapezium correction. It is important to notice that the ICs are designed for use with a DC-coupled vertical deflection stage. This is the reason why a vertical linearity alignment is not necessary (and, therefore, not available). For a particular combination of picture tube type and vertical output stage and E-W output stage, it is determined which are the required values for the settings of S-correction. These parameters can be preset via the I2C-bus and do not need any additional adjustment. The remainder of the parameters are preset with the mid-value of their control range (i.e. 1FH), or with the values obtained by previous TV set adjustments. The vertical shift control is intended for compensation of off-sets in the external vertical output stage or in the picture tube. It can be shown that without compensation these off-sets will result in a certain linearity error, especially with picture tubes that need large S-correction. The total linearity error is in 1st order approximation proportional to the value of the off-set and to the square of the S-correction needed. The necessity to use the vertical TDA837x family shift alignment depends on the expected off-sets in vertical output stage and picture tube, on the required value of the S-correction and on the demands upon vertical linearity. For adjustment of the vertical shift and vertical slope independent of each other, a special service blanking mode can be entered by setting the SBL bit HIGH. In this mode the RGB outputs are blanked during the second half of the picture. There are 2 different methods for alignment of the picture in vertical direction. Both methods make use of the service blanking mode. The first method is recommended for picture tubes that have a marking for the middle of the screen. With the vertical shift control the last line of the visible picture is positioned exactly in the middle of the screen. After this adjustment the vertical shift should not be changed. The top of the picture is placed by adjusting the vertical amplitude and the bottom by adjusting the vertical slope. The second method is recommended for picture tubes that have no marking for the middle of the screen. For this method a video signal is required in which the middle of the picture is indicated (e.g. the white line in the circle test pattern). With the vertical slope control the beginning of the blanking is positioned exactly on the middle of the picture. Then the top and bottom of the picture are placed symmetrically with respect to the middle of the screen by adjustment of the vertical amplitude and vertical shift. After this adjustment the vertical shift has the correct setting and should not be changed. If the vertical shift alignment is not required VSH should be set to its mid-value (i.e. VSH = 1FH). The top of the picture is then placed by adjusting the vertical amplitude and the bottom by adjusting the vertical slope. After the vertical picture alignment the picture is positioned in the horizontal direction by adjusting the horizontal shift. To obtain the full range of the vertical zoom function with the TDA8375 and TDA8377 the adjustment of the vertical geometry should be carried out at a nominal setting of the zoom DAC at position 19H. 1997 Jul 01 53 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family handbook, full pagewidth 70 vertical position (%) 60 50 40 30 20 10 top picture MGK296 138% 100% 75% 1/2 t 0 -10 -20 -30 -40 -50 -60 bottom picture blanking for exponential 138% time t Fig.28 Sawtooth waveform and blanking pulse of the TDA8375 and TDA8377. 104 handbook, halfpage audio output (mV) (RMS) MGK298 AVL on AVL off 14 dB 103 6 dB 25 kHz (norm) A 102 10 B 102 C D 104 103 de-emphasis (mV) (RMS) See Table 58. Fig.29 AVL characteristics of the TDA8373 and TDA8374 for 3.5 MHz standard. 1997 Jul 01 54 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family 104 handbook, halfpage audio output (mV) (RMS) AVL on AVL off MGK299 14 dB 103 6 dB 50 kHz (norm) A 102 10 102 BC D E 104 103 de-emphasis (mV) (RMS) See Table 59. Fig.30 AVL characteristics of the TDA8374 for 4.4 MHz standard. Table 58 Explanation to Fig.29 A 50 5 50 100 B 100 10 100 200 C 250 25 250 500 D 500 50 500 1000 DESCRIPTION de-emphasis pin 55 [mV (RMS)] FM swing (kHz) AVL input [mV (RMS)] external input [mV (RMS)] Table 59 Explanation to Fig.30 A 100 10 50 100 B 200 20 100 200 C 250 25 125 250 D 1000 100 500 1000 DESCRIPTION de-emphasis pin 55 [mV (RMS)] FM swing (kHz) AVL input [mV (RMS)] external input [mV (RMS)] 1997 Jul 01 55 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors INTERNAL PIN CONFIGURATION TDA837x family TSTCON 1 300 2.2 k 10 pF 15 pF sound limiter plus demodulator + 100 15 k 15 k 2 sound switch plus amplifier 25 k 4V MGK304 MGK303 Fig.31 Pin 1. Fig.32 Pin 2. 3 4 + + + + 5 6 k 6 k MGK305 Fig.33 Pins 3, 4 and 5. + 200 + 5V 7 6 300 MGK343 MGK306 Fig.34 Pin 6. Fig.35 Pin 7. 1997 Jul 01 56 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family 5V + + 8 30 300 9 MGK307 MGK308 Fig.36 Pin 8. Fig.37 Pin 9. TSTCON 10 300 + 100 k 10 pF 100 k TXT DECODER PIP 30 k + 100 11, 13, 17 Vref DUMMY CLAMP MGK309 decoder switch chroma output switch control decoder sync luma MGK310 Fig.38 Pin 10. Fig.39 Pins 11, 13 and 17. + 12, 37 analog supply 14 + GND1 MGK344 MGK333 Fig.40 Pins 12 and 37. Fig.41 Pin 14. 1997 Jul 01 57 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family + 2 k sound amplifier 300 15 100 A MGK312 + + -100 A/ +100 A filter tuning 300 16 50 k 10 pF MGK313 Fig.42 Pin 15. Fig.43 Pin 16. V/I + 10 pF + 14 k 18 200 A IL Vref = 4 V 10 A + 100 2 mA 19, 20, 21 MGK314 MGK315 Fig.44 Pin 18. Fig.45 Pins 19, 20 and 21. + Vref1 contrast control + + 22 vertical guard 1 k 4V 40 k Vref2 peak white limiting brightness control 200 A MGK316 Fig.46 Pin 22. 1997 Jul 01 58 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family + + + + + 6V 300 23, 24, 25 26 insertion + 300 + 4V 50 A MGK317 blanking MGK318 Fig.47 Pins 23, 24 and 25. Fig.48 Pin 26. + + + + + 500 6V 50 pF + 10 27 10 28 500 A 0.2 A MGK319 MGK320 Fig.49 Pin 27. Fig.50 Pin 28. + + + 31, 32 100 + 100 + 2.5 V 29, 30 MGK322 MGK321 Fig.51 Pins 29 and 30. Fig.52 Pins 31 and 32. 1997 Jul 01 59 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors + + 30 250 A 2.7 V TDA837x family + + 34, 35 R 33 3.7 V R MGK323 MGK324 pin 34: crystal = 3.58 MHz; R = 1 k pin 35: crystal = 4.43 MHz; R = 1 k Fig.53 Pin 33. Fig.54 Pins 34 and 35. + + 100 TSTCON 38 3.8 V 100 600 A MGK326 + + 400 36 + MGK325 Fig.55 Pin 36. Fig.56 Pin 38. 39 + + 30 40 protection MGK327 MGK328 Fig.57 Pin 39. Fig.58 Pin 40. 1997 Jul 01 60 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors + 5.3 V burstkey TDA837x family + J + 30 41 V blank 2.9 V 3V 2 A burstkey MGK329 Fig.59 Pin 41. + + 5.3 V flash level + 300 42 MGK330 Fig.60 Pin 42. + + J 300 43 300 4V 3.3 V 4.7 V dF HOSC 4V MGK331 (NC plus POR) Fig.61 Pin 43. 1997 Jul 01 61 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family + 45 44 GND2, connected to substrate MGK311 600 MGK332 Fig.62 Pin 44. Fig.63 Pin 45. + 100 48 + + + + 46, 47 49 MGK334 1 k 2.4 pF 100 1 k to IF amplifier MGK335 Fig.64 Pins 46 and 47. Fig.65 Pins 48 and 49. + + 300 50 3.9 V XPR 2V MGK336 J + J + 51 J MGK337 Fig.66 Pin 50. Fig.67 Pin 51. 1997 Jul 01 62 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family Iref + 52 Vref MGK338 Fig.68 Pin 52. + 1.5 mA AGC det 53 + + LSPEED NEGMOD 50 A gating 500 nA 600 A clamp MGK339 Fig.69 Pin 53. + + 55 sound switch plus amplifier TSTCON sound demodulator 54 20 k MGK340 3V MGK341 Fig.70 Pin 54. Fig.71 Pin 55. 1997 Jul 01 63 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family + 56 100 A DC stabilisation -50/50 A MGK342 Fig.72 Pin 56. 1997 Jul 01 64 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors PACKAGE OUTLINES QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.7 mm; high stand-off height TDA837x family SOT319-1 c y X 51 52 33 32 ZE A e E HE A A2 A1 Q (A 3) Lp L detail X wM pin 1 index bp 64 1 wM D HD ZD B vM B 19 vM A 20 e bp 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.3 A1 0.36 0.10 A2 2.87 2.57 A3 0.25 bp 0.50 0.35 c 0.25 0.13 D (1) 20.1 19.9 E (1) 14.1 13.9 e 1 HD 24.2 23.6 HE 18.2 17.6 L 1.95 Lp 1.0 0.6 Q 1.43 1.23 v 0.2 w 0.2 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 7 0o o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT319-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-02-04 1997 Jul 01 65 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors TDA837x family SDIP56: plastic shrink dual in-line package; 56 leads (600 mil) SOT400-1 seating plane D ME A2 A L A1 c Z e b1 wM (e 1) MH b 56 29 pin 1 index E 1 28 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 5.08 A1 min. 0.51 A2 max. 4.0 b 1.3 0.8 b1 0.53 0.40 c 0.32 0.23 D (1) 52.4 51.6 E (1) 14.0 13.6 e 1.778 e1 15.24 L 3.2 2.8 ME 15.80 15.24 MH 17.15 15.90 w 0.18 Z (1) max. 2.3 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT400-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 95-12-06 1997 Jul 01 66 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). SDIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. QFP REFLOW SOLDERING Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). 1997 Jul 01 67 TDA837x family Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary from 50 to 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheat for 45 minutes at 45 C. WAVE SOLDERING Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Short-form specification Limiting values TDA837x family This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. The data in this specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1997 Jul 01 68 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors NOTES TDA837x family 1997 Jul 01 69 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors NOTES TDA837x family 1997 Jul 01 70 Philips Semiconductors Preliminary specification I2C-bus controlled economy PAL/NTSC and NTSC TV-processors NOTES TDA837x family 1997 Jul 01 71 Philips Semiconductors - a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 0044 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580920 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Rua do Rocio 220, 5th floor, Suite 51, 04552-903 Sao Paulo, SAO PAULO - SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 829 1849 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997 Internet: http://www.semiconductors.philips.com SCA54 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 547047/1200/01/pp72 Date of release: 1997 Jul 01 Document order number: 9397 750 01808 |
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